Abstract: An optical sensor in which photo currents generated by light in the visible and infrared wavelength ranges are to be tapped separately at pn junctions of active regions. The active regions include n- or p-doping and are formed in a p-substrate 52. The optical sensor comprises a surface-near first active region 12, and a second active region 14 subjacent to the first active region 12 and forming together with the first active region 12 a pn junction 22 that is short-circuited. A third active region 20 is subjacent to the second active region 14 and forming together with the second active region a further pn junction 23. Together with a fourth active region 24 subjacent to the second active region 20, a further pn junction 25, 29 is formed together with the third active region 20 and the substrate 52.

Abstract: An optical sensor in which photo currents generated by light in the visible and infrared wavelength ranges are to be tapped separately at pn junctions of active regions. The active regions include n- or p-doping and are formed in a p-substrate 52. The optical sensor comprises a surface-near first active region 12, and a second active region 14 subjacent to the first active region 12 and forming together with the first active region 12 a pn junction 22 that is short-circuited. A third active region 20 is subjacent to the second active region 14 and forming together with the second active region a further pn junction 23. Together with a fourth active region 24 subjacent to the second active region 20, a further pn junction 25, 29 is formed together with the third active region 20 and the substrate 52.

Abstract: An optical sensor in which photo currents generated by light in the visible and infrared wavelength ranges are to be tapped separately at pn junctions of active regions. The active regions include n- or p-doping and are formed in a p-substrate 52. The optical sensor comprises a surface-near first active region 12, and a second active region 14 subjacent to the first active region 12 and forming together with the first active region 12 a pn junction 22 that is short-circuited. A third active region 20 is subjacent to the second active region 14 and forming together with the second active region a further pn junction 23. Together with a fourth active region 24 subjacent to the second active region 20, a further pn junction 25, 29 is formed together with the third active region 20 and the substrate 52.

Abstract: A light shield for shielding a light sensitive element in an image sensor comprising a primary plate located such as to shield the light sensitive element from incident light, the primary plate comprising at least one aperture and the or each aperture being associated with a light blocking structure, wherein the light blocking structure comprises a secondary plate and a wall; the wall is arranged between the primary plate and the secondary plate, and is configured to act as a light barrier to light passing between the primary plate and the secondary plate.

Abstract: A CMOS image sensor pixel (200) comprising a photosensitive element (101) for generating a charge in response to incident light; a plurality of charge storage elements (103); a plurality of transfer gates (102) for enabling the transfer of charge between the photosensitive element and an associated one of the charge storage elements; and one or more first electrical connections (201) for placing at least two of the plurality of charge storage elements in mutual electrical contact.

Abstract: A CMOS image sensor pixel (200) comprising a photo-sensitive element (101) for generating a charge in response to incident light; a plurality of charge storage elements (103); a plurality of transfer gates (102) for enabling the transfer of charge between the photosensitive element and an associated one of the charge storage elements; and one or more first electrical connections (201) for placing at least two of the plurality of charge storage elements in mutual electrical contact.

Abstract: A method for producing a semiconductor wafer, in which an optical anti-reflective layer (4) is formed on the backside of the wafer in order to optimize optical access (17) to or from CMOS devices (10) through the backside (32) of the wafer (1). The CMOS devices (10) are produced only after formation of an anti-reflective layer (4), the etching stop layers (5, 6) formed thereon, the bonding layer (7) and the carrier wafer (8) bonded thereto. After formation of the CMOS devices, the etching stop layers (5, 6), the bonding layer (7) and the bonded carrier wafer (8) are thinned and removed, at least selectively, by grinding or by means of lithography (16) or masked etching.

Abstract: An optical sensor in which photo currents generated by light in the visible and infrared wavelength ranges are to be tapped separately at pn junctions of active regions. The active regions include n- or p-doping and are formed in a p-substrate 52. The optical sensor comprises a surface-near first active region 12, and a second active region 14 subjacent to the first active region 12 and forming together with the first active region 12 a pn junction 22 that is short-circuited. A third active region 20 is subjacent to the second active region 14 and forming together with the second active region a further pn junction 23. Together with a fourth active region 24 subjacent to the second active region 20, a further pn junction 25, 29 is formed together with the third active region 20 and the substrate 52.

Abstract: A light shield for shielding a light sensitive element in an image sensor comprising a primary plate located such as to shield the light sensitive element from incident light, the primary plate comprising at least one aperture and the or each aperture being associated with a light blocking structure, wherein the light blocking structure comprises a secondary plate and a wall; the wall is arranged between the primary plate and the secondary plate, and is configured to act as a light barrier to light passing between the primary plate and the secondary plate.

Abstract: There is provided a method for fabricating an optoelectronic semiconductor device (2,27) including a layer stack (1,26) that comprises a metallization structure (7,7?) including a contact region (8,11) for electrically contacting the semiconductor device (2,27). Moreover, a dielectric layer (12) and a semiconductor layer (3) are provided. The semiconductor layer (3) comprises a functional region (6) configured as an interface for electromagnetic (visible or UV) radiation. Material in regions (17,20) above the contact region (8,11) and above the functional region (6) of the layer stack (1,26) is removed by a temporarily simultaneous etching, thereby forming two windows (24,18) for coupling the semiconductor device (2,27) to the environment, optically as well as electrically. It is an accomplishment of the invention that coupling and/or absorption losses of radiation to be analysed optically in CMOS silicon and other semiconductors is reduced at the reduced process complexity.

Abstract: A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.

Abstract: A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.

Abstract: A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.

Abstract: The invention relates to methods and devices comprising a nanostructure (2;4,4a) for improving the optical behavior of components and apparatuses and/or improving the behavior of sensors by increasing the active surface area. The nanostructure (2) is produced by means of a special RIE etching process, can be modified regarding the composition of the materials thereof, and can be provided with adequate coatings. The amount of material used for the base layer (3) can be reduced by supplying a buffer layer (406). Many applications are disclosed.

Abstract: The invention relates to processes for the production and elements (components) with a nanostructure (2; 4, 4a) for improving the optical behavior of components and devices and/or for improving the behavior of sensors by enlarging the active surface area. The nanostructure (2) is produced in a self-masking fashion by means of RIE etching and its material composition can be modified and it can be provided with suitable cover layers.

Abstract: A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.

Abstract: In an integrated circuit, a light sensitive area is protected against radiation by arranging a light blocking layer sequence (504) on top of the light sensitive area. The light blocking layer sequence comprises one or several metal layers (504a) and a silicon layer (503b, 1) for the purpose of absorption. A moth eye structure is provided on the silicon layer. Thereby, a radiation incident by reflection is minimized in such a way that also stray light can effectively be kept from the light sensitive area below the light blocking layer sequence (504).

Abstract: By means of an RIE etch process for silicon (3), a pin-type structure (4,4a) without crystal defects is formed with high aspect ratio and with nano dimensions on the surface of silicon wafers without any additional patterning measures (e-beam, interference lithography, and the like) by selecting the gas components of the etch plasma in self-organization wherein, among others, a broadband antireflective behavior is obtained that may be applicable in many fields.

Abstract: By means of an RIE etch process for silicon (3), a pin-type structure (4,4a) without crystal defects is formed with high aspect ratio and with nano dimensions on the surface of silicon wafers without any additional patterning measures (e-beam, interference lithography, and the like) by selecting the gas components of the etch plasma in self-organization wherein, among others, a broadband antireflective behaviour is obtained that may be applicable in many fields.

Abstract: In an integrated circuit, a light sensitive area is protected against radiation by arranging a light blocking layer sequence (504) on top of the light sensitive area. The light blocking layer sequence comprises one or several metal layers (504a) and a silicon layer (503b, 1) for the purpose of absorption. A moth eye structure is provided on the silicon layer. Thereby, a radiation incident by reflection is minimized in such a way that also stray light can effectively be kept from the light sensitive area below the light blocking layer sequence (504).