Abstract: Methods and systems are provided for mixing component materials and dispensing a gradient product comprising a continuously varied composition of matter. The method includes delivering, by multiple dispensing devices actuated by a motor, component material to a connector where each of multiple connector inputs receives component material from a respective one of the multiple dispensing devices. The component material is forwarded to a mixing tube connected to a single output of the connector. The mixing tube receives the component material from each of the multiple dispensing devices via the connector and mixes the component material. A dispensing nozzle connected to the mixing tube, receives a continuously varying mixture of materials from the mixing tube and dispenses the continuously varying mixture of materials onto a collection bed to form a gradient product comprising a continuously varying composition of matter. An electronic processor controls the varied composition of matter of the gradient product.

Abstract: A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.

Abstract: A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.