Patents by Inventor Daniel Gallant

Daniel Gallant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CASCADED PLL FOR REDUCING LOW-FREQUENCY DRIFT IN HOLDOVER MODE
    Publication number: 20140225653
    Abstract: A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.
    Type: Application
    Filed: February 13, 2013
    Publication date: August 14, 2014
    Applicant: SILICON LABORATORIES INC.
    Inventors: Susumu Hara, Adam B. Eldredge, Jeffrey S. Batchelor, Daniel Gallant
  • Cascaded PLL for reducing low-frequency drift in holdover mode
    Patent number: 8791734
    Abstract: A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: July 29, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Susumu Hara, Adam D. Eldredge, Jeffrey S. Batchelor, Daniel Gallant