Abstract: The independent claims of this patent signify a concise description of embodiments. A method is provided for reducing a size of an emulation clock tree for a circuit design. The method comprises identifying a fan-in cone of an input of a sequential element of the circuit design; identifying one or more fan-in cone sequential elements which do not directly affect the input of the sequential element; and removing the one or more identified fan-in cone sequential elements of the fan-in cone from the emulation clock tree. This Abstract is not intended to limit the scope of the claims.

Abstract: A search for a regular expression in a tree hierarchy, includes, in part, searching for a match to the regular expression in a first subtree defined by a first node name, recording information about the first subtree if there is no match, determining whether a second subtree defined by a second node name is identical to the first node, skipping search of the second subtree if the second subtree is determined to be identical and prefix equivalent, with respect to the regular expression, to the first subtree. The second subtree is determined to be prefix equivalent to the first subtree when for any string s, a first prefix defined by a concatenation of the first node name and the string s results in a match if and only if a second prefix defined by a concatenation of the second node name and the string s results in a match.

Abstract: The independent claims of this patent signify a concise description of embodiments. A method of performing hardware emulation of a circuit design is presented. The method includes partitioning a first portion of the circuit design to a first configurable logic chip of a hardware emulator, adding a selection circuit to the circuit design in the first configurable logic chip, and selecting one of a first signal or a second signal during a first clock cycle. The first signal and the second signal are used in the circuit design. The method further includes storing a first value associated with the selected signal during a second clock cycle, and sending the first value to an output pin of the first configurable logic chip during a third clock cycle. This Abstract is not intended to limit the scope of the claims.

Abstract: Configuring a hardware system includes providing a first data representative of a first assignment of a multitude of wires to a multitude of physical connections between a multitude of logic circuits of the hardware system, and transforming the first data into a second data representative of a second assignment of the multitude of wires to the multitude of physical connections. The transforming includes calculating a multitude of latencies each associated with a selected one of the multitude of wires, and assigning a first subset of the multitude of wires to at least one of the multitude of physical connections in accordance with a first improvement goal. The transforming causes the value of each one of the multitude of latencies that are associated with the first subset to be less than or equal to the first improvement goal, when the second data is used to configure the hardware system.

Abstract: Configuring a hardware system includes providing a first data representative of a first assignment of a multitude of wires to a multitude of physical connections between a multitude of logic circuits of the hardware system, and transforming the first data into a second data representative of a second assignment of the multitude of wires to the multitude of physical connections. The transforming includes calculating a multitude of latencies each associated with a selected one of the multitude of wires, and assigning a first subset of the multitude of wires to at least one of the multitude of physical connections in accordance with a first improvement goal. The transforming causes the value of each one of the multitude of latencies that are associated with the first subset to be less than or equal to the first improvement goal, when the second data is used to configure the hardware system.

Abstract: A computer-implemented method, apparatus and computer program product for debugging programs, the method comprising: displaying a graphic waveform showing values of one or more state variables of a computer program being debugged in two or more points in time; receiving a user selection from points in time, of an indication to a selected point in time in execution from the graphic waveform; and resuming within a debugger an execution state of the computer program associated with the selected point in time.

Abstract: Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include a state variable AF for one or more states of the target model, wherein AF(S) represents value of the state variable AF at state S; and solving the translated version of the target model that satisfies predetermined constrains.

Abstract: A computer-implemented method, apparatus and computer program product for debugging programs, the method comprising: displaying a graphic waveform showing values of one or more state variables of a computer program being debugged in two or more points in time; receiving a user selection from points in time, of an indication to a selected point in time in execution from the graphic waveform; and resuming within a debugger an execution state of the computer program associated with the selected point in time.

Abstract: A temporal assertion of a computer program may be defined based on a temporal property. A checker may be generated to monitor the temporal assertion and indicate upon a violation thereof. The checker may be operatively coupled to a debugging module operative to execute the computer program in a debugging session. The execution may be paused in response to an indication from the checker of a violation of the temporal assertion, while continuing the debugging session. A user may then review the state of the computer program to assess what caused the assertion to fail and whether such a violation indicates the presence of a bug or not.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include a state variable AF for one or more states of the target model, wherein AF(S) represents value of the state variable AF at state S; and solving the translated version of the target model that satisfies predetermined constrains.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: A method for design verification includes running a simulation of a design in a simulation environment, which comprises a stimuli generator for providing inputs to the design during the simulation. Respective measures of quality are computed for at least some of the simulation states in a sequence of states generated by the environment. State data are saved with respect to at least one of the simulation states. The state data include indications both of the respective simulated state and of the respective environment state. Responsively to the respective measures of quality, the saved state data are recalled so as to restart the simulation from the at least one of the simulation states by returning the design to the respective simulated state and returning the simulation environment to the respective environment state.

Abstract: A test coverage tool provides output that identifies differences between the actual coverage provided by a test suite run on a program under test and the coverage criteria (e.g., the coverage criteria required by the test/development team management). The output from the test coverage tool is generated in the same language that was used to write the coverage criteria that are input to an automated test generator to create the test cases which form the test suite. As a result, the output from the coverage tool can be input back into the automated test generator to cause the generator to revise the test cases to correct the inadequacies. This allows iterative refinement of the test suite automatically, enabling automated test generation to be more effectively and efficiently used with more complex software and more complex test generation inputs.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: A leak detection system includes a trace gas leak detector having a wireless base unit, and a handheld wireless remote unit to generate an alphanumeric display of leak rate measured by the leak detector, in response to leak detector information received by wireless link from the leak detector. The remote unit may include a wireless transceiver to communicate with the wireless base unit of the leak detector, a display unit and a controller, responsive to the received leak detector information, to generate the display on the display unit. The remote unit may be configured to control the leak detector and may be configured to display a leak detector operating mode.

Abstract: A method for verification includes providing an implementation model, which defines model states of a target system and model transitions between the model states, and providing a specification of the target system, including properties that the system is expected to obey. A tableau is created from the specification, the tableau defining tableau states with tableau transitions between the tableau states in accordance with the properties. The tableau transitions are compared to the model transitions to determine whether a discrepancy exists therebetween.

Abstract: A synchronization method including running a system (725) having multiple agents (730 and 780) in parallel operation, the multiple agents each having at least one path (732) to a common bus (734). A bus arbitration mechanism (728) is used to synchronize between said multiple agents in accordance with a predetermined scheme, including blocking (310) at least one individual agent's path to the common bus (734) if said scheme indicates (315) that said individual agent is not to be activated, and restoring (320) said at least one individual agent's path (730) to the common bus (734) once said scheme indicates that said individual agent (730) can be activated.

Abstract: A test coverage tool provides output that identifies differences between the actual coverage provided by a test suite run on a program under test and the coverage criteria (e.g., the coverage criteria required by the test/development team management). The output from the test coverage tool is generated in the same language that was used to write the coverage criteria that are input to an automated test generator to create the test cases which form the test suite. As a result, the output from the coverage tool can be input back into the automated test generator to cause the generator to revise the test cases to correct the inadequacies. This allows iterative refinement of the test suite automatically, enabling automated test generation to be more effectively and efficiently used with more complex software and more complex test generation inputs.