Abstract: The independent claims of this patent signify a concise description of embodiments. A method is provided for reducing a size of an emulation clock tree for a circuit design. The method comprises identifying a fan-in cone of an input of a sequential element of the circuit design; identifying one or more fan-in cone sequential elements which do not directly affect the input of the sequential element; and removing the one or more identified fan-in cone sequential elements of the fan-in cone from the emulation clock tree. This Abstract is not intended to limit the scope of the claims.

Abstract: A search for a regular expression in a tree hierarchy, includes, in part, searching for a match to the regular expression in a first subtree defined by a first node name, recording information about the first subtree if there is no match, determining whether a second subtree defined by a second node name is identical to the first node, skipping search of the second subtree if the second subtree is determined to be identical and prefix equivalent, with respect to the regular expression, to the first subtree. The second subtree is determined to be prefix equivalent to the first subtree when for any string s, a first prefix defined by a concatenation of the first node name and the string s results in a match if and only if a second prefix defined by a concatenation of the second node name and the string s results in a match.

Abstract: The independent claims of this patent signify a concise description of embodiments. A method of performing hardware emulation of a circuit design is presented. The method includes partitioning a first portion of the circuit design to a first configurable logic chip of a hardware emulator, adding a selection circuit to the circuit design in the first configurable logic chip, and selecting one of a first signal or a second signal during a first clock cycle. The first signal and the second signal are used in the circuit design. The method further includes storing a first value associated with the selected signal during a second clock cycle, and sending the first value to an output pin of the first configurable logic chip during a third clock cycle. This Abstract is not intended to limit the scope of the claims.

Abstract: Configuring a hardware system includes providing a first data representative of a first assignment of a multitude of wires to a multitude of physical connections between a multitude of logic circuits of the hardware system, and transforming the first data into a second data representative of a second assignment of the multitude of wires to the multitude of physical connections. The transforming includes calculating a multitude of latencies each associated with a selected one of the multitude of wires, and assigning a first subset of the multitude of wires to at least one of the multitude of physical connections in accordance with a first improvement goal. The transforming causes the value of each one of the multitude of latencies that are associated with the first subset to be less than or equal to the first improvement goal, when the second data is used to configure the hardware system.

Abstract: Configuring a hardware system includes providing a first data representative of a first assignment of a multitude of wires to a multitude of physical connections between a multitude of logic circuits of the hardware system, and transforming the first data into a second data representative of a second assignment of the multitude of wires to the multitude of physical connections. The transforming includes calculating a multitude of latencies each associated with a selected one of the multitude of wires, and assigning a first subset of the multitude of wires to at least one of the multitude of physical connections in accordance with a first improvement goal. The transforming causes the value of each one of the multitude of latencies that are associated with the first subset to be less than or equal to the first improvement goal, when the second data is used to configure the hardware system.

Abstract: A filament assembly includes a core and a filament. At least a central portion of the filament is disposed on the core. At least the central portion may be straight or may have a high-resistance configuration such as one in which the filament follows a path that changes direction. A thermionically emissive layer may be disposed on the core so as to encapsulate at least the central portion. The filament assembly may be utilized in any application requiring the production of electrons.

Abstract: A computer-implemented method, apparatus and computer program product for debugging programs, the method comprising: displaying a graphic waveform showing values of one or more state variables of a computer program being debugged in two or more points in time; receiving a user selection from points in time, of an indication to a selected point in time in execution from the graphic waveform; and resuming within a debugger an execution state of the computer program associated with the selected point in time.

Abstract: Tracer gas leak detection is provided by a calibration system with a gas leak detector having a test port for receiving a sample containing a tracer gas and coupled to a vacuum pump; a calibrated leak for a calibration sample containing the tracer gas; a mass filter coupled to the test port for receiving the test sample in an operating mode, coupled to the calibrated leak through a calibrated leak valve for receiving the calibration sample in a calibration mode, having controllable transmission of the tracer gas and providing a filtered sample; detector detecting the tracer gas in the filtered sample; a programmable gain element providing a measured value of leak rate in response to the detector signal; and a controller configured, in response to a mode control signal, to operate the leak detector in the calibration mode over two or more working ranges using the calibrated leak.

Abstract: Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include a state variable AF for one or more states of the target model, wherein AF(S) represents value of the state variable AF at state S; and solving the translated version of the target model that satisfies predetermined constrains.

Abstract: A trace gas sensing apparatus includes a cathode, an anode, a vacuum enclosure, and a membrane. The anode coaxially surrounds the cathode, wherein the cathode and the anode define an annular ionization chamber. The vacuum enclosure surrounds the cathode and the anode and includes a gas inlet fluidly communicating with the ionization chamber. The membrane is coupled to the gas inlet in a sealed manner and is permselective to trace gas. The apparatus may further include circuitry for applying a negative voltage potential to the cathode and for measuring an ion current signal generated by the cathode, and a magnet assembly for generating a magnetic field in the ionization chamber. The cathode may include an elongated member located along a longitudinal axis, and first and second end plates orthogonal to the longitudinal axis.

Abstract: A computer-implemented method, apparatus and computer program product for debugging programs, the method comprising: displaying a graphic waveform showing values of one or more state variables of a computer program being debugged in two or more points in time; receiving a user selection from points in time, of an indication to a selected point in time in execution from the graphic waveform; and resuming within a debugger an execution state of the computer program associated with the selected point in time.

Abstract: A temporal assertion of a computer program may be defined based on a temporal property. A checker may be generated to monitor the temporal assertion and indicate upon a violation thereof. The checker may be operatively coupled to a debugging module operative to execute the computer program in a debugging session. The execution may be paused in response to an indication from the checker of a violation of the temporal assertion, while continuing the debugging session. A user may then review the state of the computer program to assess what caused the assertion to fail and whether such a violation indicates the presence of a bug or not.

Abstract: A trace gas sensing apparatus includes a cathode, an anode, a vacuum enclosure, and a membrane. The anode coaxially surrounds the cathode, wherein the cathode and the anode define an annular ionization chamber. The vacuum enclosure surrounds the cathode and the anode and includes a gas inlet fluidly communicating with the ionization chamber. The membrane is coupled to the gas inlet in a sealed manner and is permselective to trace gas. The apparatus may further include circuitry for applying a negative voltage potential to the cathode and for measuring an ion current signal generated by the cathode, and a magnet assembly for generating a magnetic field in the ionization chamber. The cathode may include an elongated member located along a longitudinal axis, and first and second end plates orthogonal to the longitudinal axis.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include a state variable AF for one or more states of the target model, wherein AF(S) represents value of the state variable AF at state S; and solving the translated version of the target model that satisfies predetermined constrains.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: Tracer gas leak detection is provided by a calibration system with a gas leak detector having a test port for receiving a sample containing a tracer gas and coupled to a vacuum pump; a calibrated leak for a calibration sample containing the tracer gas; a mass filter coupled to the test port for receiving the test sample in an operating mode, coupled to the calibrated leak through a calibrated leak valve for receiving the calibration sample in a calibration mode, having controllable transmission of the tracer gas and providing a filtered sample; detector detecting the tracer gas in the filtered sample; a programmable gain element providing a measured value of leak rate in response to the detector signal; and a controller configured, in response to a mode control signal, to operate the leak detector in the calibration mode over two or more working ranges using the calibrated leak.

Abstract: Mass spectrometers for trace gas leak detection and methods for operating mass spectrometers are provided. The mass spectrometer includes an ion source to ionize trace gases, such as helium, a magnet to deflect the ions and a detector to detect the deflected ions. The ion source includes an electron source, such a filament. The method includes operating the electron source at an electron accelerating potential relative to an ionization chamber sufficient to ionize the trace gas but insufficient to form undesired ions, such as triply charged carbon.

Abstract: A mass spectrometer includes a main magnet having spaced-apart polepieces which define a gap, the main magnet producing a magnetic field in the gap, an ion source to generate ions and to accelerate the ions into the magnetic field in the gap, the ion source located outside the gap, and an ion detector to detect a selected species of the ions generated by the ion source and deflected by the magnetic field. The ion detector is located in the gap at a natural focus point of the selected species of ions. The mass spectrometer may be used in a trace gas leak detector.