Patents by Inventor Daniel Gitlin
Daniel Gitlin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190385995Abstract: A tier of a 3D circuit comprising: one or more macro circuits, each macro circuit comprising a plurality of macro cells arranged in an array, the macro cells being separated from each other by spaces; and interconnection vias positioned in the spaces between the macro cells.Type: ApplicationFiled: June 17, 2019Publication date: December 19, 2019Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Hughes Metras, Fabien Clermidy, Daniel Gitlin, Didier Lattard, Sébastien Thuries, Pascal Vivet
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Patent number: 8436656Abstract: Some embodiments provide an integrated circuit (‘IC’) that includes at least first and second circuits operating at a first voltage. The IC includes, between the first and second circuits, a direct connection comprising a third circuit for transmitting a signal from the first circuit to the second circuit at a second voltage that is lower than the first voltage. At least one of the first and second circuits is a configurable circuit for configurably performing operations.Type: GrantFiled: January 7, 2009Date of Patent: May 7, 2013Assignee: Tabula, Inc.Inventors: Daniel Gitlin, Martin Voogel, Jason Redgrave, Matt Crowley
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Publication number: 20110267103Abstract: Some embodiments provide an integrated circuit (‘IC’) that includes at least first and second circuits operating at a first voltage. The IC includes, between the first and second circuits, a direct connection comprising a third circuit for transmitting a signal from the first circuit to the second circuit at a second voltage that is lower than the first voltage. At least one of the first and second circuits is a configurable circuit for configurably performing operations.Type: ApplicationFiled: January 7, 2009Publication date: November 3, 2011Applicant: Tabula, Inc.Inventors: Daniel Gitlin, Martin Voogel, Jason Redgrave, Matt Crowley
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Patent number: 7956385Abstract: A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.Type: GrantFiled: July 30, 2010Date of Patent: June 7, 2011Assignee: Xilinx, Inc.Inventors: Yuhao Luo, Shuxian Wu, Xin X. Wu, Jae-Gyung Ahn, Deepak K. Nayak, Daniel Gitlin
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Patent number: 7936006Abstract: An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric structure underlies the channel region of a MOS device, as well as the source and drain extensions.Type: GrantFiled: October 6, 2005Date of Patent: May 3, 2011Assignee: Xilinx, Inc.Inventors: Yuhao Luo, Deepak Kumar Nayak, Daniel Gitlin
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Patent number: 7839693Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.Type: GrantFiled: January 7, 2010Date of Patent: November 23, 2010Assignee: Xilinix, Inc.Inventors: Sunhom Paak, Boon Y. Ang, Hsung J. Im, Daniel Gitlin
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Patent number: 7772093Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.Type: GrantFiled: October 26, 2007Date of Patent: August 10, 2010Assignee: Xilinx, Inc.Inventors: Yuhao Luo, Shuxian Wu, Xin X. Wu, Jae-Gyung Ahn, Deepak Kumar Nayak, Daniel Gitlin
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Patent number: 7688639Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.Type: GrantFiled: October 12, 2007Date of Patent: March 30, 2010Assignee: Xilinx, Inc.Inventors: Sunhom Paak, Boon Yong Ang, Hsung Jai Im, Daniel Gitlin
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Patent number: 7687797Abstract: A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.Type: GrantFiled: August 24, 2005Date of Patent: March 30, 2010Assignee: Xilinx, Inc.Inventors: James Karp, Daniel Gitlin, Shahin Toutounchi, Michael G. Ahrens, Jongheon Jeong
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Publication number: 20090108337Abstract: A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.Type: ApplicationFiled: October 26, 2007Publication date: April 30, 2009Applicant: Xilinx, Inc.Inventors: Yuhao Luo, Shuxian Wu, Xin X. Wu, Jae-Gyung Ahn, Deepak Kumar Nayak, Daniel Gitlin
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Patent number: 7294888Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.Type: GrantFiled: September 30, 2005Date of Patent: November 13, 2007Assignee: Xilinx, Inc.Inventors: Sunhom Paak, Boon Yong Ang, Hsung Jai Im, Daniel Gitlin
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Layout correction algorithms for removing stress and other physical effect induced process deviation
Patent number: 7032194Abstract: A method for dealing with process specific physical effects applies dimensional modifications to an IC layout to compensate for performance variations caused by the physical effects. Because the dimensional modifications harmonize the performance of the actual IC with the performance of the IC model, time-consuming re-verification operations are not required. Current drive variations caused by shallow trench isolation (STI) stress can be compensated for by adjusting the gate dimensions of the affected transistors to increase or decrease current drive as necessary. Such physical effect compensation can be applied before, after, or even concurrently with optical proximity correction (OPC). The dimensional modifications for physical effect compensation can also be incorporated into an OPC engine.Type: GrantFiled: February 19, 2003Date of Patent: April 18, 2006Assignee: Xilinx, Inc.Inventors: Shih-Cheng Hsueh, Xiao-Jie Yuan, Daniel Gitlin -
Patent number: 6740936Abstract: A transistor with ballast resistor formed between the transistor drain and the drain contact is formed by masking regions of the ballast resistor to increase resistivity and thus reduce required area. The invention achieves this without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size for the same ESD requirement or allows better ESD protection for a given die size.Type: GrantFiled: April 25, 2002Date of Patent: May 25, 2004Assignee: Xilinx, Inc.Inventors: Daniel Gitlin, James Karp, Jongheon Jeong, Jan L. de Jong
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Patent number: 6645802Abstract: An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate.Type: GrantFiled: June 8, 2001Date of Patent: November 11, 2003Assignee: Xilinx, Inc.Inventors: Sheau-Suey Li, Shahin Toutounchi, Michael J. Hart, Xin X. Wu, Daniel Gitlin
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Patent number: 6621325Abstract: Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.Type: GrantFiled: September 18, 2001Date of Patent: September 16, 2003Assignee: Xilinx, Inc.Inventors: Michael J. Hart, Steven P. Young, Daniel Gitlin, Hua Shen, Stephen M. Trimberger
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Patent number: 6549458Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.Type: GrantFiled: October 25, 2001Date of Patent: April 15, 2003Assignee: Xilinx, Inc.Inventors: Kameswara K. Rao, Martin L. Voogel, James Karp, Shahin Toutounchi, Michael J. Hart, Daniel Gitlin, Kevin T. Look, Jongheon Jeong, Radko G. Bankras
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Publication number: 20030053335Abstract: Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.Type: ApplicationFiled: September 18, 2001Publication date: March 20, 2003Applicant: Xilinx, Inc.Inventors: Michael J. Hart, Steven P. Young, Daniel Gitlin, Hua Shen, Stephen M. Trimberger
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Patent number: 6522582Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells.Type: GrantFiled: April 19, 2000Date of Patent: February 18, 2003Assignee: Xilinx, Inc.Inventors: Kameswara K. Rao, Martin L. Voogel, James Karp, Shahin Toutounchi, Michael J. Hart, Daniel Gitlin, Kevin T. Look, Jongheon Jeong, Radko G. Bankras
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Patent number: 6268639Abstract: An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate.Type: GrantFiled: February 11, 1999Date of Patent: July 31, 2001Assignee: Xilinx, Inc.Inventors: Sheau-Suey Li, Shahin Toutounchi, Michael J. Hart, Xin X. Wu, Daniel Gitlin
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Patent number: 6266269Abstract: A three terminal non-volatile memory element includes a standard (low voltage) CMOS transistor, i.e. a storage transistor, having a drain coupled to a read bit line and a source connected to ground. The storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. Of importance, in submicron technology, the source and drain regions of the storage transistor merge, thereby providing a highly reliable, conductive path. Thus, the state of the memory cell can be advantageously read solely via the read bit line.Type: GrantFiled: June 7, 2000Date of Patent: July 24, 2001Assignee: Xilinx, Inc.Inventors: James Karp, Daniel Gitlin, Shahin Toutounchi