Abstract: A video decoder in which the video source clock is generated entirely in the digital domain is disclosed herein. By creating a virtual version of the source clock in a numeric oscillator, the amount of noise in the system is substantially reduced. Furthermore, by transferring the digitized video signal, sampled with an asynchronous crystal clock, into the source clock domain, the accuracy of the brightness (amplitude) and color (phase) information can be greatly enhanced.

Abstract: Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is provided to a digital output formatter. The digital output formatter is driven by the output clock, which may be locked to the source clock if desired. The output clock is developed by a clock generator which may be one of several different types, including a fractional N synthesizer, a direct digital synthesizer or a puncture clock.

Abstract: A video decoder in which 1) resolution quality can be improved for a given bit count analog-to-digital converter, 2) a lower bit count analog-to-digital converter can be used with substantially similar quality or 3) a combination of improved resolution quality with a lower bit count analog-to-digital converter can be done. In the preferred embodiment, a DC bias is added to the video signal after the sync portion of the composite signal has been received and prior to the active video being received. This bias is then removed after the end of the active video period. By applying this bias, the DC voltage level of the video signals is actually reduced, so that the full scale value of the analog-to-digital conversion process can also be reduced. Thus, compared to using an unbiased signal, increased A/D converter resolution is obtained. In an alternative embodiment, the sync portion can be biased upwardly during the front porch and then be returned during the back porch.

Abstract: A time-based, digital FM demodulator circuit receives a stream of digital samples corresponding to an analog FM waveform. The samples are provided to a zero crossing detector, which allows a counter to determine a number of clock cycles between zero crossings. The resolution of this coarse period determination is further refined by an intercept calculation, which further localizes the zero crossing of the FM waveform based on interpolation between samples on either side of the zero crossing. Accuracy of the period determination may be further enhanced by use of a sinusoidal correction filter, which minimizes error caused by the linear interpolation performed on the sinusoidal waveform. Although the FM demodulator circuit is particularly suitable for demodulation of the chroma component of a SECAM video signal, it may advantageously be applied in a wide variety of FM demodulation applications.