Abstract: A method and apparatus are provided for implementing power control in multi-voltage input/output (I/O) circuits. First current biasing devices are provided for creating a first constant bias current. Second current biasing devices are provided for creating a second bias current. The second current biasing devices are activated at a first voltage and are deactivated at a second voltage. The first voltage is less than the second voltage.

Abstract: A high speed voltage level shifter and phase splitter circuit is provided. The voltage level shifter and phase splitter circuit includes an input signal and a first input inverter stage that receives the input signal and provides an inverted delayed out of phase signal to the input signal. A buffer stage receives the input signal and provides a buffered delayed in phase signal to the input signal. A first constant current source is coupled between the first input inverter stage and the buffer stage. A first output inverter stage is coupled to the first constant current source and provides a voltage level shifted and out of phase signal to the input signal. A second constant current source is coupled between the first input inverter stage and the buffer stage having an opposite polarity as the first constant current source. A second output inverter stage is coupled to the second constant current source and providing a voltage level shifted and in phase signal to the input signal.

Abstract: A mixed voltage output driver includes an output sensing circuit that senses an output voltage at an output terminal and generates a voltage signal that corresponds to a voltage level at the output terminal. Next, an impedance selection circuit receives the voltage signal and generates a control signal in response to the output voltage having a higher logical uplevel than the mixed voltage output driver. The control signal is then received by an adjustable drive impedance circuit that is also coupled to an input terminal of the mixed voltage output driver and, in response thereto, the adjustable drive impedance circuit modifies an output drive impedance of the mixed voltage output driver. In another advantageous embodiment, the mixed voltage output driver only determines if the output voltage at the output terminal is at a logical uplevel before adjusting the output drive impedance.

Abstract: A boundary configuration (Common Input/output CIO) for Generalized Scan Designs (GSD) in a single clock chip design includes at least one generalized scan design internal latch; a boundary scan clock input to the internal latch; an input/output cell connected to the internal latch; and at least one control line between the internal latch and the input/output cell. The CIO GSD is arranged and configured to operate in various modes including a function mode, a RUNBIST/INTEST/LBIST mode, an EXTEST/WIRETEST mode, a SAMPLE/PRELOAD mode, etc. In a different version, a MUX controller is connected to the internal latch. The MUX controller selects data from one of at least two control lines and sending the selected data to at least one internal logic unit of the chip for a test operation.

Abstract: A communication system for an array of DASD includes a plurality of loop resiliency circuits and a plurality of selection circuits. The DASD array includes a plurality of DASD slots. Each DASD slot may receive a DASD, and each DASD receives power from a regulator. The loop resiliency circuits form at least a first communication path. Each loop resiliency circuit is associated with one of the DASD slots and selectively includes the associated DASD slot in the first communication path based on a selection signal. The plurality of selection circuits are also associated with one of the DASD slots; and therefore, are also associated with one of the plurality of loop resiliency circuits. Each selection circuit is connected to the associated DASD slot and receives output from the regulator in the associated DASD slot. Based on the regulator output, or a lack thereof, the selection circuit generates a selection signal for the associated loop resiliency circuit.

Abstract: The present invention is a driver circuit for interfacing electronic components which have different supply voltages. The driver circuit includes a source terminal for receiving a source voltage, an output terminal connected to an off-chip electronic component, and a pull up circuit disposed between the source and output terminals for providing a field effect controlled current path between the source terminal and the output terminal. The pull up circuit includes a first transistor in series with a second transistor, the second transistor providing overvoltage stress relief for the first transistor.