Patents by Inventor Daniel H. Doyle
Daniel H. Doyle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8446762Abstract: One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.Type: GrantFiled: March 25, 2011Date of Patent: May 21, 2013Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Gordon A. Haller, Daniel H. Doyle
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Patent number: 8194454Abstract: An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.Type: GrantFiled: August 9, 2011Date of Patent: June 5, 2012Assignee: Round Rock Research, LLCInventor: Daniel H. Doyle
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Publication number: 20120002474Abstract: An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.Type: ApplicationFiled: August 9, 2011Publication date: January 5, 2012Applicant: ROUND ROCK RESEARCH, LLCInventor: Daniel H. Doyle
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Patent number: 8004897Abstract: An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.Type: GrantFiled: August 27, 2010Date of Patent: August 23, 2011Assignee: Round Rock Research, LLCInventor: Daniel H. Doyle
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Publication number: 20110171802Abstract: One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.Type: ApplicationFiled: March 25, 2011Publication date: July 14, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Sanh D. Tang, Gordon Haller, Daniel H. Doyle
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Patent number: 7944743Abstract: One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.Type: GrantFiled: August 7, 2009Date of Patent: May 17, 2011Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Gordon A. Haller, Daniel H. Doyle
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Publication number: 20100322003Abstract: An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.Type: ApplicationFiled: August 27, 2010Publication date: December 23, 2010Applicant: MICRON TECHNOLOGY, INC.Inventor: Daniel H. Doyle
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Patent number: 7808824Abstract: An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.Type: GrantFiled: May 26, 2009Date of Patent: October 5, 2010Assignee: Micron Technology, Inc.Inventor: Daniel H. Doyle
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Publication number: 20090311845Abstract: One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.Type: ApplicationFiled: August 7, 2009Publication date: December 17, 2009Applicant: Micron Technology, Inc.Inventors: Sanh D. Tang, Gordon Haller, Daniel H. Doyle
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Publication number: 20090231918Abstract: An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.Type: ApplicationFiled: May 26, 2009Publication date: September 17, 2009Applicant: Micron Technology, Inc.Inventor: Daniel H. Doyle
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Patent number: 7589995Abstract: One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.Type: GrantFiled: September 7, 2006Date of Patent: September 15, 2009Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Gordon Haller, Daniel H. Doyle
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Patent number: 7539062Abstract: An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.Type: GrantFiled: December 20, 2006Date of Patent: May 26, 2009Assignee: Micron Technology, Inc.Inventor: Daniel H. Doyle
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Patent number: 7501676Abstract: A memory cell, array and device include cross-shaped active areas and polysilicon gate areas disposed over arm portions of adjacent cross-shaped active areas. The polysilicon gate areas couple word lines with capacitors associated with each arm portion of the cross-shaped active areas. Buried digit lines are coupled to body portions of the cross-shaped active areas. The word lines and digit lines provide a unique contact to each capacitor of the array of memory cells. Each memory cell has an area of 5F2. An electronic system and method for fabricating a memory cell are also disclosed.Type: GrantFiled: March 25, 2005Date of Patent: March 10, 2009Assignee: Micron Technology, Inc.Inventor: Daniel H. Doyle
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Patent number: 7499325Abstract: Some embodiments include a device having memory cells coupled to a well of a semiconductor substrate, and a select transistor coupled between the memory cells and a bit line of the device. The device may have a first circuit to raise a well voltage of the well from a first well voltage level to a second well voltage level during an erase operation. The first circuit may hold the well at the second well voltage level for a time interval during the erase operation. The device may have a second circuit to raise a voltage of the gate of the select transistor from a first gate voltage level to a second gate voltage level, which may be lower than the second well voltage level. The second circuit may hold the gate at the second gate voltage level for a time interval during the erase operation. Other embodiments including additional apparatus, systems, and methods are disclosed.Type: GrantFiled: December 21, 2006Date of Patent: March 3, 2009Assignee: Intel CorporationInventors: Daniel H. Doyle, Mark Helm, Andrei Mihnea
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Publication number: 20080151637Abstract: An interleaved memory programming and verification method, device and system includes a memory array includes first and second memory banks of memory cells. The memory device further includes a controller configured to concurrently program a first data into the first memory bank and a second data into the second memory bank using iterative programming and verification operations in each of the first and second memory banks with the programming and verification operations in the second memory bank being offset from the programming and verification operations in the first memory bank.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Inventor: Daniel H. Doyle
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Publication number: 20080151646Abstract: Some embodiments include a device having memory cells coupled to a well of a semiconductor substrate, and a select transistor coupled between the memory cells and a bit line of the device. The device may have a first circuit to raise a well voltage of the well from a first well voltage level to a second well voltage level during an erase operation. The first circuit may hold the well at the second well voltage level for a time interval during the erase operation. The device may have a second circuit to raise a voltage of the gate of the select transistor from a first gate voltage level to a second gate voltage level, which may be lower than the second well voltage level. The second circuit may hold the gate at the second gate voltage level for a time interval during the erase operation. Other embodiments including additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Inventors: Daniel H. Doyle, Mark Helm, Andrei Mihnea
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Publication number: 20080061346Abstract: One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.Type: ApplicationFiled: September 7, 2006Publication date: March 13, 2008Inventors: Sanh D. Tang, Gordon Haller, Daniel H. Doyle