Patents by Inventor Daniel H. Liu

Daniel H. Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10733039
    Abstract: This disclosure relates to testing of integrated artificial intelligence (AI) circuit with embedded memory to improve effective chip yield and to mapping addressable memory segments of the embedded memory to multilayer AI networks at the network level, layer level, parameter level, and bit level based on bit error rate (BER) of the addressable memory segments. The disclosed methods and systems allows for deployment of one or more multilayer AI networks in an AI circuit with sufficient model accuracy even when the embedded memory has an overall BER higher than a preferred overall threshold.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 4, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Daniel H. Liu, Wenhan Zhang, Hualiang Yu
  • Publication number: 20200201697
    Abstract: This disclosure relates to testing of integrated artificial intelligence (AI) circuit with embedded memory to improve effective chip yield and to mapping addressable memory segments of the embedded memory to multilayer AI networks at the network level, layer level, parameter level, and bit level based on bit error rate (BER) of the addressable memory segments. The disclosed methods and systems allows for deployment of one or more multilayer AI networks in an AI circuit with sufficient model accuracy even when the embedded memory has an overall BER higher than a preferred overall threshold.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Daniel H. LIU, Wenhan Zhang, Hualiang Yu
  • Publication number: 20200193280
    Abstract: This disclosure relates to artificial intelligence (AI) circuits with embedded memory for storing trained AI model parameters. The embedded memory cell structure, device profile, and/or fabrication process are designed to generate binary data access asymmetry and error rate asymmetry between writing binary zeros and binary ones that are adapted to and compatible with a binary data asymmetry of the trained model parameters and/or a bit-inversion tolerance asymmetry of the AI model between binary zeros and ones. The disclosed method and system improves predictive accuracy and memory error tolerance without significantly reducing an overall memory error rate and without relying on memory cell redundancy and error correction codes.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Hualiang Yu, Wenhan Zhang, Daniel H. Liu
  • Patent number: 10672455
    Abstract: An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: June 2, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong, Daniel H. Liu
  • Patent number: 10590376
    Abstract: A system and method for conditioning a tissue are provided. The system includes a substrate, a plurality of microwells formed in the substrate, and a microsphere associated with each of the plurality of microwells. The system also includes a pair of flexible pillars within each of the plurality of microwells. Each flexible pillar includes a first end bonded to a respective microwell and at least one flexible pillar has a second end bonded to the microsphere. The flexible pillars are configured to deflect when exposed to a magnetic field to controllably stretch microtissue spanning the flexible pillars.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: March 17, 2020
    Assignee: The Johns Hopkins University
    Inventors: Daniel H. Reich, Fan Xu, Ruogang Zhao, Alan S. Liu, Tristin Metz, Yu Shi
  • Patent number: 10563431
    Abstract: A cable lock including a lock body having a locking mechanism with a locked state and an unlocked state. A ceramic body cable includes a plurality of nested ceramic bodies and a cord, wherein each one of the plurality of ceramic bodies includes a center portion having an aperture. Each aperture of the plurality of nested ceramic bodies forms a channel through which the cord is positioned. Each of the ceramic bodies also includes a projection and a space such that the projection of one of the ceramic bodies overlaps the space of an adjacent ceramic body. A mesh sleeve is positioned on an exterior of the ceramic body cable and a shrunken heat shrinkable tube is positioned over the mesh sleeve. The combined ceramic body cable, mesh sleeve, and shrunken heat shrinkable tube are coupled to the lock body.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: February 18, 2020
    Assignee: Schlage Lock Company LLC
    Inventors: Douglas A. Holmes, Daniel H. Kindstrand, Jonah S. Eidman, Gideon Hou, Thomas Y. Liu, Ryan T. Stolz
  • Publication number: 20200042888
    Abstract: This disclosure relates to a self-contained and self-sufficient edge device capable of performing processing data sets using a convolutional neural network model without relying on any backend servers. In particularly, the edge device may include non-volatile memory cells for storing a full set of trained model parameters from the convolutional neural network model. The non-volatile memory cells may be based on magnetic random access memory cells and may be embedded on the same semiconductor substrate with a convolutional neural network logic circuit dedicated to parallel forward propagation calculation.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Hualiang YU, Chyu-Jiuh Torng, Daniel H. Liu
  • Publication number: 20190378950
    Abstract: In one aspect, optoelectronic devices are described herein. In some implementations, an optoelectronic device comprises a photovoltaic cell. The photovoltaic cell comprises a space-charge region, a quasi-neutral region, and a low bandgap absorber region (LBAR) layer or an improved transport (IT) layer at least partially positioned in the quasi-neutral region of the cell.
    Type: Application
    Filed: August 12, 2019
    Publication date: December 12, 2019
    Applicant: The Boeing Company
    Inventors: Richard R. King, Christopher M. Fetzer, Daniel C. Law, Xing-Quan Liu, William D. Hong, Kenneth M. Edmondson, Dimitri D. Krut, Joseph C. Boisvert, Nasser H. Karam
  • Publication number: 20190363131
    Abstract: This disclosure relates to embedding memories into with logic circuits for improving memory access speed and reducing power consumption. In particular, memories of distinct types embedded with logic circuits on a same semiconductor substrate are disclosed. These memories may include static random access memory, magnetoresistive random access memory, and various types of resistive random access memory. These different types of memories may be combined to form an embedded memory subsystem that provide distinct memory persistency, programmability, and access characteristics tailored for storing different type of data in, e.g., application involving convolutional neural networks.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 28, 2019
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Daniel H. Liu
  • Patent number: 10439091
    Abstract: In one aspect, optoelectronic devices are described herein. In some implementations, an optoelectronic device comprises a photovoltaic cell. The photovoltaic cell comprises a space-charge region, a quasi-neutral region, and a low bandgap absorber region (LBAR) layer or an improved transport (IT) layer at least partially positioned in the quasi-neutral region of the cell.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: October 8, 2019
    Assignee: THE BOEING COMPANY
    Inventors: Richard R. King, Christopher M. Fetzer, Daniel C. Law, Xing-Quan Liu, William D. Hong, Kenneth M. Edmondson, Dimitri D. Krut, Joseph C. Boisvert, Nasser H. Karam
  • Publication number: 20190267072
    Abstract: An integrated circuit includes an artificial intelligence (AID) logic and an embedded memory coupled to the AID logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Applicant: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong, Daniel H. LIU
  • Patent number: 10353214
    Abstract: Optical stacks including a grating structure that generates diffraction in two in-plane dimensions. The optical stacks may include two gratings, which may be one-directional or two-directional. The optical stacks are suitable for reducing sparkle in displays.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: July 16, 2019
    Assignees: 3M Innovative Properties Company, Corning Incorporated
    Inventors: Brett J. Sitter, Marc D. Radcliffe, Thomas R. Hoffend, Jr., Daniel W. Hennen, Michael L. Steiner, Lan H. Liu, Jacques Gollier, James Andrew West, Ellen Marie Kosik Williams
  • Patent number: 10347317
    Abstract: An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 9, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong, Daniel H. Liu
  • Publication number: 20190194979
    Abstract: A cable lock including a lock body having a locking mechanism with a locked state and an unlocked state. A ceramic body cable includes a plurality of nested ceramic bodies and a cord, wherein each one of the plurality of ceramic bodies includes a center portion having an aperture. Each aperture of the plurality of nested ceramic bodies forms a channel through which the cord is positioned. Each of the ceramic bodies also includes a projection and a space such that the projection of one of the ceramic bodies overlaps the space of an adjacent ceramic body. A mesh sleeve is positioned on an exterior of the ceramic body cable and a shrunken heat shrinkable tube is positioned over the mesh sleeve. The combined ceramic body cable, mesh sleeve, and shrunken heat shrinkable tube are coupled to the lock body.
    Type: Application
    Filed: February 5, 2019
    Publication date: June 27, 2019
    Inventors: Douglas A. Holmes, Daniel H. Kindstrand, Jonah S. Eidman, Gideon Hou, Thomas Y. Liu, Ryan T. Stolz
  • Publication number: 20190180173
    Abstract: An integrated circuit may include an AI logic circuit, and an embedded one-time programmable (OTP) MRAM memory electrically coupled to the AI logic circuit. The embedded OTP MRAM memory may include multiple storage cells, one or more reference resistors, and a memory-reading circuit for determining the state of each storage cell. The reading circuit may include: a multiplexer configured to electrically couple each storage cell to a reference resistor; a source line selectively providing an input electrical signal to each storage cell to generate a first output signal; a driving circuit providing an input electrical signal to the reference resistor to generate a second output signal; and a comparator configured to compare the first output signal and the second output signal to generate an output signal that indicates the state of each storage cell. Each reference resistor may be shared among multiple storages in an array or multiple storage arrays.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 13, 2019
    Inventors: Chyu-Jiuh Torng, Daniel H. Liu
  • Publication number: 20190108868
    Abstract: An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.
    Type: Application
    Filed: October 5, 2017
    Publication date: April 11, 2019
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong, Daniel H. Liu