Abstract: A power transistor chip package includes a power transistor chip having a first load electrode on a first side, a second load electrode on a second (opposite) side, and a control electrode. The power transistor chip is disposed on a chip pad, with the first side facing the pad and the first load electrode electrically connected to the pad. An encapsulation body encapsulates the power transistor chip and includes a footprint side, a top (opposite) side, and side faces extending between the footprint and top sides. A first package load terminal is electrically connected to the first load electrode. Part I and part II second package load terminals are both electrically connected directly to the second load electrode. A package control terminal is electrically connected to the control electrode. The part I and part II second package load terminals are aligned with opposite sides faces of the encapsulation body.

Abstract: A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.

Abstract: A semiconductor device includes: a semiconductor substrate having a bulk oxygen concentration of at least 6×1017 cm?3; an epitaxial layer on a first side of the semiconductor substrate, the epitaxial layer and the semiconductor substrate having a common interface; a superjunction semiconductor device structure in the epitaxial layer; and an interface region extending from the common interface into the semiconductor substrate to a depth of at least 10 ?m. A mean oxygen concentration of the interface region is lower than the bulk oxygen concentration of the semiconductor substrate.

Abstract: A semiconductor device includes: a semiconductor substrate having a bulk oxygen concentration of at least 6×1017 cm?3; an epitaxial layer on a first side of the semiconductor substrate, the epitaxial layer and the semiconductor substrate having a common interface; a superjunction semiconductor device structure in the epitaxial layer; and an interface region extending from the common interface into the semiconductor substrate to a depth of at least 10 ?m. A mean oxygen concentration of the interface region is lower than the bulk oxygen concentration of the semiconductor substrate.

Abstract: A method for forming semiconductor device includes providing a semiconductor substrate having an initial surface oxygen concentration in a surface region of less than 6×1017 cm?3, forming an epitaxial layer on a first side of the semiconductor substrate, and implanting dopants into the epitaxial layer. An optional thermal anneal is carried out prior to forming the epitaxial layer and/or a thermal treatment is carried out after implanting dopants.

Abstract: A method for forming semiconductor device includes providing a semiconductor substrate having an initial surface oxygen concentration in a surface region of less than 6×1017 cm?3, forming an epitaxial layer on a first side of the semiconductor substrate, and implanting dopants into the epitaxial layer. An optional thermal anneal is carried out prior to forming the epitaxial layer and/or a thermal treatment is carried out after implanting dopants.