Patents by Inventor Daniel H. Morris
Daniel H. Morris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11734174Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.Type: GrantFiled: September 19, 2019Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Huichu Liu, Tanay Karnik, Tejpal Singh, Yen-Cheng Liu, Lavanya Subramanian, Mahesh Kumashikar, Sri Harsha Choday, Sreenivas Subramoney, Kaushik Vaidyanathan, Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Patent number: 11735652Abstract: Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.Type: GrantFiled: September 28, 2017Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Seiyon Kim, Uygar E. Avci, Joshua M. Howard, Ian A. Young, Daniel H. Morris
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Patent number: 11522130Abstract: A routing structure is disclosed. A first wiring line coupled to a programming access device and a routing block driver and receiver enabling device and a second wiring line coupled to a programming access device and a routing block driver and receiver enabling device. An insulator-metal-transistor device that includes a top electrode, a middle electrode and a bottom electrode, coupled at the intersection of the first wiring line and the second wiring line.Type: GrantFiled: June 28, 2018Date of Patent: December 6, 2022Assignee: Intel CorporationInventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Patent number: 11502103Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a “FE capacitor”). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.Type: GrantFiled: August 28, 2018Date of Patent: November 15, 2022Assignee: Intel CorporationInventors: Daniel H. Morris, Seiyon Kim, Uygar E. Avci, Ian A. Young
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Patent number: 11495596Abstract: An integrated circuit structure comprises a substrate having a memory region of and an adjacent logic region. A first N type well (Nwell) is formed in the substrate for the memory region and a second Nwell formed in the substrate for the logic region. A plurality of memory transistors in the memory region and a plurality of logic transistors are in the logic region, wherein ones the memory transistors include a floating gate over a channel, and a source and a drain on opposite sides of the channel. A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors for state retention during power gating.Type: GrantFiled: September 28, 2018Date of Patent: November 8, 2022Assignee: Intel CorporationInventors: Uygar E. Avci, Daniel H. Morris, Ian A. Young
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Patent number: 11450675Abstract: Described herein are one access transistor and one ferroelectric capacitor (1T-1FE-CAP) memory cells in diagonal arrangements, as well as corresponding methods and devices. When access transistors of memory cells are implemented as FinFETs, then, in a first diagonal arrangement, memory cells are arranged so that the BLs for the cells are diagonal with respect to the fins of the access transistors of the cells, while the WLs for the cells are perpendicular to the fins. In a second diagonal arrangement, memory cells are arranged so that the fins of the access transistors of the cells are diagonal with respect to the WLs for the cells, while the BLs for the cells are perpendicular to the WLs. Such diagonal arrangements may advantageously allow achieving high layout densities of 1T-1FE-CAP memory cells and may benefit from the re-use of front-end transistor process technology with relatively minor adaptations.Type: GrantFiled: September 14, 2018Date of Patent: September 20, 2022Assignee: Intel CorporationInventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Publication number: 20220231035Abstract: Described herein are anti-ferroelectric (AFE) memory cells and corresponding methods and devices. For example, in some embodiments, an AFE memory cell disclosed herein includes a capacitor employing an AFE material between two capacitor electrodes. Applying a voltage to one electrode of such capacitor allows boosting the charge at the other electrode, where nonlinear behavior of the AFE material between the two electrodes may advantageously manifest itself in that, for a given voltage applied to the first electrode, a factor by which the charge is boosted at the second electrode of the capacitor may be substantially different for different values of charge at that electrode before the boost. Connecting the second capacitor electrode to a storage node of the memory cell may then allow boosting the charge on the storage node so that different logic states of the memory cell become more clearly resolvable, enabling increased retention times.Type: ApplicationFiled: April 5, 2022Publication date: July 21, 2022Applicant: Intel CorporationInventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Patent number: 11355505Abstract: Techniques and mechanisms to provide a memory array comprising a 1T1C (one transistor and one capacitor) based memory cell. In an embodiment, the memory cell comprises a transistor, fabricated on a backend of a die, and a capacitor which includes a ferroelectric material. The transistor of the 1T1C memory cell is a vertical transistor. In another embodiment, the capacitor is positioned vertically over the transistor.Type: GrantFiled: September 29, 2017Date of Patent: June 7, 2022Assignee: Intel CorporationInventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Patent number: 11355504Abstract: Described herein are anti-ferroelectric (AFE) memory cells and corresponding methods and devices. For example, in some embodiments, an AFE memory cell disclosed herein includes a capacitor employing an AFE material between two capacitor electrodes. Applying a voltage to one electrode of such capacitor allows boosting the charge at the other electrode, where nonlinear behavior of the AFE material between the two electrodes may advantageously manifest itself in that, for a given voltage applied to the first electrode, a factor by which the charge is boosted at the second electrode of the capacitor may be substantially different for different values of charge at that electrode before the boost. Connecting the second capacitor electrode to a storage node of the memory cell may then allow boosting the charge on the storage node so that different logic states of the memory cell become more clearly resolvable, enabling increased retention times.Type: GrantFiled: May 31, 2018Date of Patent: June 7, 2022Assignee: Intel CorporationInventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Patent number: 11232832Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.Type: GrantFiled: October 1, 2020Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Patent number: 11171145Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.Type: GrantFiled: June 22, 2018Date of Patent: November 9, 2021Assignee: Intel CorporationInventors: Sou-Chi Chang, Uygar Avci, Daniel H. Morris, Seiyon Kim, Ashish V. Penumatcha, Ian A. Young
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Patent number: 11037614Abstract: Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line; a second multiplexer coupled to the source-line; a first driver coupled to the first multiplexer; a second driver coupled to the second multiplexer; and a current source coupled to the first and second drivers.Type: GrantFiled: July 23, 2018Date of Patent: June 15, 2021Assignee: Intel CorporationInventors: Huichu Liu, Sasikanth Manipatruni, Ian A. Young, Tanay Karnik, Daniel H. Morris, Kaushik Vaidyanathan
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Patent number: 11004868Abstract: Memory field-effect transistors and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor substrate and a ferroelectric gate insulator of a memory field-effect transistor formed within a trench having walls defined by spacers and a base defined by the semiconductor substrate. The apparatus further includes a gate conductor formed on the ferroelectric gate insulator. The ferroelectric gate insulator is to separate a bottom surface of the gate conductor and the substrate.Type: GrantFiled: March 22, 2017Date of Patent: May 11, 2021Assignee: Intel CorporationInventors: Seiyon Kim, Uygar E. Avci, Joshua M. Howard, Ian A. Young, Daniel H. Morris
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Patent number: 10998339Abstract: Described herein are ferroelectric memory cells and corresponding methods and devices. For example, in some embodiments, a ferroelectric memory cell disclosed herein includes one access transistor and one ferroelectric transistor (1T-1FE-FET cell). The access transistor is coupled to the ferroelectric transistor by sharing its source/drain terminal with that of the ferroelectric transistor and is used for both READ and WRITE access to the ferroelectric transistor.Type: GrantFiled: December 12, 2016Date of Patent: May 4, 2021Assignee: Intel CorporationInventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Publication number: 20210089448Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.Type: ApplicationFiled: September 19, 2019Publication date: March 25, 2021Applicant: Intel CorporationInventors: Huichu Liu, Tanay Karnik, Tejpal Singh, Yen-Cheng Liu, Lavanya Subramanian, Mahesh Kumashikar, Sri Harsha Chodav, Sreenivas Subramoney, Kaushik Vaidyanathan, Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Patent number: 10901486Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.Type: GrantFiled: April 15, 2019Date of Patent: January 26, 2021Assignee: Intel CorporationInventors: Kaushik Vaidyanathan, Daniel H. Morris, Uygar E. Avci, Ian A. Young, Tanay Karnik, Huichu Liu
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Publication number: 20210020233Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.Type: ApplicationFiled: October 1, 2020Publication date: January 21, 2021Inventors: Daniel H. MORRIS, Uygar E. AVCI, Ian A. YOUNG
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Patent number: 10886286Abstract: An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.Type: GrantFiled: September 28, 2018Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Ashish Verma Penumatcha, Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Patent number: 10832761Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.Type: GrantFiled: January 2, 2020Date of Patent: November 10, 2020Assignee: Intel CorporationInventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Publication number: 20200321446Abstract: Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode.Type: ApplicationFiled: September 28, 2017Publication date: October 8, 2020Inventors: Seiyon KIM, Uygar E. AVCI, Joshua M. HOWARD, Ian A. YOUNG, Daniel H. MORRIS