Patents by Inventor Daniel H. SAARI

Daniel H. SAARI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Elimination of probability of bit errors in successive approximation register (SAR) analog-to-digital converter (ADC) logic
    Patent number: 11888498
    Abstract: Systems and methods related to successive approximation register (SAR) analog-to-digital converters (ADCs) are provided. A method for performing successive approximation registers (SAR) analog-to-digital conversion includes comparing, using a comparator, a first digital-to-analog (DAC) output voltage to a sampled analog input voltage to generate a comparison result including a first positive output and a first negative output; and gating, using gating logic circuitry, at least one of the first positive output or the first negative output of the comparator to next logic circuitry, the gating based at least in part on a digital feedback comprising information associated with at least one of an opposite polarity of the first positive output or an opposite polarity of the first negative output.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: January 30, 2024
    Assignee: Analog Devices International Unlimited Company
    Inventors: Daniel H. Saari, Lewis F. Lahr
  • ELIMINATION OF PROBABILITY OF BIT ERRORS IN SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) LOGIC
    Publication number: 20230231569
    Abstract: Systems and methods related to successive approximation register (SAR) analog-to-digital converters (ADCs) are provided. A method for performing successive approximation registers (SAR) analog-to-digital conversion includes comparing, using a comparator, a first digital-to-analog (DAC) output voltage to a sampled analog input voltage to generate a comparison result including a first positive output and a first negative output; and gating, using gating logic circuitry, at least one of the first positive output or the first negative output of the comparator to next logic circuitry, the gating based at least in part on a digital feedback comprising information associated with at least one of an opposite polarity of the first positive output or an opposite polarity of the first negative output.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 20, 2023
    Applicant: Analog Devices International Unlimited Company
    Inventors: Daniel H. SAARI, Lewis F. LAHR