Patents by Inventor DANIEL HADAD

DANIEL HADAD has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240151517
    Abstract: A method for estimating a geometrical shape of an optical fiber (106) includes transmitting (102) into the optical fiber an input optical signal that excites in the optical fiber multiple propagation modes. An output optical signal, which is output from the optical fiber in response to the input optical signal, is recombined with a reference signal derived from the input optical signal, so as to produce a recombined optical signal. The recombined optical signal is detected (108), and the geometrical shape of the optical fiber (106) is estimated based on the detected recombined optical signal.
    Type: Application
    Filed: May 15, 2022
    Publication date: May 9, 2024
    Inventors: Avishay Eyal, Alon Bahabad, Daniel Marima, Barak Hadad, Nadav Magal
  • Patent number: 8782478
    Abstract: A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: July 15, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Richard K. Eguchi, Daniel Hadad, Chen He, Katrina M. Prosperi, Jon W. Weilmann, II
  • Publication number: 20140040687
    Abstract: A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.
    Type: Application
    Filed: October 8, 2013
    Publication date: February 6, 2014
    Inventors: Richard K. Eguchi, Daniel Hadad, Chen He, Katrina M. Prosperi, Jon W. Weilmann, II
  • Patent number: 8572445
    Abstract: A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: October 29, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Richard K. Eguchi, Daniel Hadad, Chen He, Katrina M. Prosperi, Jon W. Weilemann, II
  • Patent number: 8516213
    Abstract: A defect resistant EEPROM emulator (110) uses one or more redundant and/or spare blocks (213) in addition to active and alternate blocks (211, 212) and stores a duplicate copy of EEPROM data records either in the active and redundant blocks or in duplicate rows in the active block to ensure that EEPROM emulation can continue without data loss in the event a catastrophic failure occurs within a block.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: August 20, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chen He, Richard K. Eguchi, Daniel Hadad, Katrina M. Prosperi, Jon W. Weilemann, II
  • Publication number: 20120131262
    Abstract: A defect resistant EEPROM emulator (110) uses one or more redundant and/or spare blocks (213) in addition to active and alternate blocks (211, 212) and stores a duplicate copy of EEPROM data records either in the active and redundant blocks or in duplicate rows in the active block to ensure that EEPROM emulation can continue without data loss in the event a catastrophic failure occurs within a block.
    Type: Application
    Filed: November 24, 2010
    Publication date: May 24, 2012
    Inventors: Chen He, Richard K. Eguchi, Daniel Hadad, Katrina M. Prosperi, Jon W. Weilemann, II
  • Publication number: 20120072794
    Abstract: A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 22, 2012
    Inventors: RICHARD K. EGUCHI, DANIEL HADAD, CHEN HE, KATRINA M. PROSPERI, JON W. WEILEMANN, II