Abstract: A pattern recognition system includes a filter bank, coupled via rectifying elements to integrators which are coupled via different weighting elements to the summing nodes of a summing amplifier. The filter bank, integrators, and weighting elements include switched capacitors enabling the manufacture of the filters, rectifiers, integrators and weighting elements on a monolithic integrated circuit chip. The frequencies at which the capacitors are switched are programmable enabling the system to be easily "retuned".

Abstract: A classifying system for determining with which group of a plurality of groups of reference file words a data word most closely compares and comprising a plurality of groups of comparison means each constructed to simultaneously and individually compare a different group of file words with said data word to produce a comparison pulse for each comparison of said data word with a file word. Means are provided for identifying each group of file words in which the comparison of not more than one file word with the data word produces a comparison pulse whose amplitude exceeds, in a given direction of polarity, the predetermined amplitude of a threshold signal, and further for identifying each of said one file words.

Abstract: A class of logic circuits in which different types of current switching logic gates are connected to different nodes of a current summing network for concurrently producing different logic functions of the same input variables. In one embodiment, N single-input current switches forming a threshold logic gate are operated with their inputs parallelling respective ones of an N-input current switch forming an emitter-coupled logic (ECL) OR-gate. An output current of the ECL gate is combined with the out-of-phase output currents of the threshold gate in a first current summing network, comprised of at least two resistors, for producing different logic functions of the signals applied to the N inputs. The in-phase output currents of the threshold gate are supplied to a second summing network for producing still different logic functions of the input signals. The different logic functions produced at the different nodes of the two summing networks may be further combined (e.g.