Abstract: A furniture assembly (1; 101) comprising: —an upper module (3; 103); —a lower module (5; 105); and —a wall part (7; 107) which is arranged for being provided between the upper and the lower module when the furniture assembly (1; 101) is mounted in a room in a mounting position with the upper module (3; 103) provided above the lower module (5; 105), wherein said wall part (7; 107) is pre-mounted to either the upper module (3; 103) or the lower module (5; 105).

Abstract: A furniture assembly (1; 101) comprising: —an upper module (3; 103); —a lower module (5; 105); and —a wall part (7; 107) which is arranged for being provided between the upper and the lower module when the furniture assembly (1; 101) is mounted in a room in a mounting position with the upper module (3; 103) provided above the lower module (5; 105), wherein said wall part (7; 107) is pre-mounted to either the upper module (3; 103) or the lower module (5; 105).

Abstract: One embodiment of the present invention provides a technique for automatic diagnosis of regression test failures. Initially, an automatic regression test system provides the test results per configuration for a revision of the device under test. Next, each failing test is analyzed in conjunction with the information in the version control system that is used to manage the device under test in order to conclude what additional revisions that needs to be tested for each test and configuration in order to find the earliest failing revision. Next, a request is issued to the automated regression test system which performs the requested tests and provides back a list of test results. Next, another analysis takes places and if the earliest failing revision cannot be concluded for each failing test and configuration then another request is issues to the automated regression test system. This continues until the earliest failing revision can be concluded for each failing test and configuration.

Abstract: One embodiment of the present invention provides a technique for automatic diagnosis of regression test failures. Initially, an automatic regression test system provides the test results per configuration for a revision of the device under test. Next, each failing test is analyzed in conjunction with the information in the version control system that is used to manage the device under test in order to conclude what additional revisions that needs to be tested for each test and configuration in order to find the earliest failing revision. Next, a request is issued to the automated regression test system which performs the requested tests and provides back a list of test results. Next, another analysis takes places and if the earliest failing revision cannot be concluded for each failing test and configuration then another request is issues to the automated regression test system. This continues until the earliest failing revision can be concluded for each failing test and configuration.

Abstract: The present invention relates to a method, device, and system for managing verification of configurable hardware and software. The solution according to the present invention solves this by applying a matrix-like method of handling test and verification parameter combinations and interacting with a user using a browser like interface for simple and fast selection of coverage.

Abstract: The present invention relates to a method, device, and system for managing verification of configurable hardware and software. The solution according to the present invention solves this by applying a matrix-like method of handling test and verification parameter combinations and interacting with a user using a browser like interface for simple and fast selection of coverage.

Abstract: A microprocessor architecture including a unified cache debug unit. A debug unit on the processor chip receives data/command signals from a unit of the execute stage of the multi-stage instruction pipeline of the processor and returns information to the execute stage unit. The cache debug unit is operatively connected to both instruction and data cache units of the microprocessor. The memory subsystem of the processor may be accessed by the cache debug unit through either of the instruction or data cache units. By unifying the cache debug in a separate structure, the need for redundant debug structure in both cache units is obviated. Also, the unified cache debug unit can be powered down when not accessed by the instruction pipeline, thereby saving power.

Abstract: A method and apparatus for reducing power consumption within a pipelined processor. In one embodiment, the method of the invention comprises defining an instruction which invokes a “sleep mode” within the processor and pipeline; inserting the instruction into the pipeline; decoding and executing the instruction, stalling the pipeline in response to the sleep mode instruction; disabling memory in response to the sleep mode instruction; and awaking the core from sleep mode based on the occurrence of a predetermined event. Methods for structuring core pipeline logic and extension instructions to reduce core power consumption under various conditions are described. Methods and apparatus for synthesizing logic implementing the aforementioned methodology are also disclosed.