Abstract: In one embodiment, there is provided a tree feeding system for use with tree handling equipment, the tree feeding system including: a housing having a frame and at least one arm; a plurality of tree feeding wheels arranged with at least one wheel on the frame and at least one wheel on the at least one arm; and a hydraulic circuit for driving the tree feeding wheels, wherein the hydraulic circuit is configured such that wheels on the frame are driven in series and wheels on the arm are driven in series. In another embodiment, the hydraulic circuit is configured such that wheels on one side (e.g. left hand side) of the housing are driven in series and wheels on an opposite side (e.g. right hand side) of the housing are driven in series but wheels on the frame are mechanically connected by a universal joint.

Abstract: An apparatus includes at least one node device to host a computing cluster, and at least one processor to generate a UI providing guidance through a set of configuration settings for the computing cluster, wherein, for each configuration setting that is received as an input during configuration, the at least one processor is caused to: perform a check of the set of configuration settings to determine whether the received configuration setting creates a conflict among the set of configuration settings; and in response to a determination that the received configuration setting creates a conflict among the set of configuration settings, perform operations including generate an indication of the conflict for presentation by the UI, and receive a change to a configuration setting as an input from the input device.

Abstract: In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns. The SRAM device further comprises a plurality of column decoders, each associated with a column group of the plurality of column groups. In some embodiments, the controller may be configured to read the local columns included in the column group by, for a given local column, sensing a voltage difference on a corresponding pair of bit lines, in a rearranged sequential order that is different from a physical sequential order of the plurality of local columns.

Abstract: There is provided a method for treating or reducing the effects of fructose intolerance and health problems associated with excessive fructose intake by administration of glucose isomerase. Other embodiments are also disclosed.

Abstract: An electric motor-brake assembly includes a housing within which a rotor assembly, a stator assembly, and a brake assembly are disposed. The brake assembly is operable between an engaged state and a disengaged state. The rotor assembly is axially movable within the housing and is supported by bearings supporting both radial and axial loads. When the motor stator is de-energized, the brake assembly is in the engaged state to prevent the rotor assembly from rotating in at least one rotational direction. When the motor stator is energized, the brake assembly is in the disengaged state such that the rotor assembly is free to rotate. The brake assembly can include a friction pack that is engaged and disengaged by axial displacement of the rotor assembly.

Abstract: An apparatus includes at least one node device to host a computing cluster, and at least one processor to generate a UI providing guidance through a set of configuration settings for the computing cluster, wherein, for each configuration setting that is received as an input during configuration, the at least one processor is caused to: perform a check of the set of configuration settings to determine whether the received configuration setting creates a conflict among the set of configuration settings; and in response to a determination that the received configuration setting creates a conflict among the set of configuration settings, perform operations including generate an indication of the conflict for presentation by the UI, and receive a change to a configuration setting as an input from the input device.

Abstract: An apparatus includes at least one node device to host a computing cluster, and at least one processor to: use at least one of a level of resource observed to be consumed by operation of the computing cluster or a level of performance observed to be provided by operation of the computing cluster as an input to a pre-existing cluster model to derive a predicted level; compare the predicted level to a corresponding observed level of resource consumed or performance provided; and in response to the predicted level not matching the observed level to within a pre-selected degree, derive a new cluster model from observations of the operation of the computing cluster, and generate a prompt to perform repeat the configuration of the computing cluster using the new cluster model in place of the pre-existing cluster model to generate a new set of configuration settings for the computing cluster.

Abstract: An apparatus includes at least one node device to host a computing cluster, and at least one processor to: use at least one of a level of resource observed to be consumed by operation of the computing cluster or a level of performance observed to be provided by operation of the computing cluster as an input to a pre-existing cluster model to derive a predicted level; compare the predicted level to a corresponding observed level of resource consumed or performance provided; and in response to the predicted level not matching the observed level to within a pre-selected degree, derive a new cluster model from observations of the operation of the computing cluster, and generate a prompt to perform repeat the configuration of the computing cluster using the new cluster model in place of the pre-existing cluster model to generate a new set of configuration settings for the computing cluster.

Abstract: A fleet management system dispatches autonomous electric vehicles (AEVs) as on-demand power sources. The fleet management system receives a request for a power source including a location and data describing the amount of power requested. The fleet management system selects an AEV of the fleet to service the request based on the relative locations of the AEVs to the requested location, and based on the amount of power requested. The fleet management system instructs the selected AEV to drive to the location and supply power. The fleet management system instructs the selected AEV to disconnect and return to the charging station, and may instruct another AEV to continue fulfilling the request if additional power is needed.

Abstract: A computer implemented method for managing virtual processor pools includes identifying a set of available system resources, defining a set of virtual resource pools, assigning one or more system resources of the set of identified system resources to one or more virtual pools of the set of virtual resource pools, creating a plurality of logical partitions within a first virtual resource pool of the set of virtual resource pools, wherein each logical partition of the plurality of logical partitions specifies a weight relative to other partitions in the first virtual resource pool, receiving a request for additional resources from the first virtual resource pool, and allowing the first virtual resource pool to access an unused resource from a second virtual resource pool of the set of virtual resource pools. A computer program product and computer system corresponding to the method are also disclosed herein.

Abstract: System on a Chip (SoC) integrated circuits are configured to reduce Static Random-Access Memory (SRAM) power leakage. For example, SoCs configured to reduce SRAM power leakage may form part of an artificial reality system including at least one head mounted display. Power switching logic on the SoC includes a first power gating transistor that supplies a first, higher voltage to an SRAM array when the SRAM array is in an active state, and a third power gating transistor that isolates a second power gating transistor from the first, higher voltage when the SRAM array is in the active state. The second power gating transistor further supplies a second, lower voltage to the SRAM array when the SRAM array is in a deep retention state, such that SRAM power leakage is reduced in the deep retention state.

Abstract: Waste chute devices and methods for using the same are provided. In some embodiments, a method for operating waste chutes comprises: receiving, using a hardware processor of a waste chute device, an identity associated with a user of the waste chute device; in response to receiving the identity associated with the user, allowing, using the hardware processor, a door of the waste chute device to be opened; determining, using the hardware processor, a number of items and at least one type associated with the items that have been placed in an opening of the waste chute device; determining, using the hardware processor, that the door of the waste chute device has been closed; updating, using the hardware processor, information associated with the user based on the number of items and the at least one type of items that have been placed in the opening of the waste chute device; and providing, using the hardware processor, the user with the updated information.

Abstract: A micro-light emitting diode (micro-LED) display backplane includes a plurality of macro-pixels. Each macro-pixel includes: a contiguous two-dimensional (2-D) array of bitcells storing display data bits for driving a set of micro-LEDs of a 2-D array of micro-LEDs; and drive circuits configured to generate, based on the display data bits stored in the contiguous 2-D array of bitcells, pulse-width modulated (PWM) drive signals for driving the set of micro-LEDs of the 2-D array of micro-LEDs. In one example, the plurality of macro-pixels is grouped into a plurality of sub-arrays, where each sub-array of the plurality of sub-arrays includes a set of macro-pixels and a local periphery circuit next to the set of macro-pixels. The local periphery circuit includes, for example, a buffer, a repeater, a clock gating circuit for gating an input clock signal to the sub-array, and/or a sub-array decoder for selecting the sub-array.

Abstract: A fleet management system dispatches autonomous electric vehicles (AEVs) as on-demand power sources. The fleet management system receives a request for a power source including a location and data describing the amount of power requested. The fleet management system selects an AEV of the fleet to service the request based on the relative locations of the AEVs to the requested location, and based on the amount of power requested. The fleet management system instructs the selected AEV to drive to the location and supply power. The fleet management system instructs the selected AEV to disconnect and return to the charging station, and may instruct another AEV to continue fulfilling the request if additional power is needed.

Abstract: An SRAM controller for performing sequential accesses using internal ports that operate concurrently on different rows. Each internal port includes a row address strobe (RAS) timer that generates clock signals controlling the timing of operations during a RAS phase in which word line decoding is performed once for a group of bit cells being accessed. The RAS phase can involve additional conditioning operations, such as precharging of local bits lines associated with the group of bit cells. The RAS phase is followed by an input/output (IO) phase in which individual bit cells are accessed in sequential address order using a column select signal generated by an IO timer. The RAS phase of a first internal port can be at least partially overlapped by the IO phase of a second internal port to hide the RAS latency of the first internal port. The IO timer can be shared among internal ports.

Abstract: In some embodiments, a system comprises a static random access memory (SRAM) device and a controller. The SRAM device comprises a bit cell array comprising a plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns. The SRAM device further comprises a plurality of column decoders, each associated with a column group of the plurality of column groups. In some embodiments, the controller may be configured to read the local columns included in the column group by, for a given local column, sensing a voltage difference on a corresponding pair of bit lines, in a rearranged sequential order that is different from a physical sequential order of the plurality of local columns.

Abstract: In some embodiments, an apparatus comprises: a static random access memory (SRAM) device. The SRAM device may have a bit cell array comprising a plurality of bit cells, the plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column of the plurality of columns operatively coupled to a pair of bit lines. The apparatus may comprise a controller configured to: assert a word line associated with a row; perform a sequence of write operations while the word line remains asserted, each write operation corresponding to a bit cell associated with a different column of the plurality of columns and the row, wherein the word line has an elevated voltage relative to a non-elevated voltage during at least a portion of the sequence of write operations; and de-assert the word line after the sequence of write operations are performed.

Abstract: A display device includes a silicon wafer including digital circuits, a micro-light emitting diode (micro-LED) wafer including an array of micro-LEDs, and an indium-gallium-zinc-oxide (IGZO) layer between the silicon wafer and the micro-LED wafer and including analog circuits. The digital circuits are characterized by a first operating supply voltage and are configured to generate digital control signals based on digital display data of an image frame. The analog circuits are characterized by a second operating supply voltage higher than the first operating supply voltage. The analog circuits includes analog storage devices configured to storing analog signals, and transistors controlled by the digital control signals and the analog signals to generate drive currents for driving the array of micro-LEDs. The digital circuits on the silicon wafer or the analog circuits in the IGZO layer include level-shifting circuits at interfaces between the digital circuits and the analog circuits.

Abstract: Medical devices are disclosed. For example, a medical device includes an elongated member. The medical device includes a hole forming surface along a portion of the elongated member. The medical device includes an open cell element in physical communication with the elongated member. The open cell element is configured to house at least a first portion of a biocompatible substance.