Patents by Inventor Daniel Hou

Daniel Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11817839
    Abstract: A single-crystal bulk acoustic wave resonators with better performance and better manufacturability and a process for fabricating the same are described. A low-acoustic-loss layer of one or more single-crystal and/or poly-crystal piezoelectric materials is epitaxially grown and/or physically deposited on a surrogate substrate, followed with the formation of a bottom electrode and then a support structure on a first side of the piezoelectric layer. The surrogate substrate is subsequently removed to expose a second side of the piezoelectric layer that is opposite to the first side. A top electrode is then formed on the second side of the piezoelectric layer, followed by further processes to complete the BAW resonator and filter fabrication using standard wafer processing steps. In some embodiments, the support structure has a cavity or an acoustic mirror adjacent the first electrode layer to minimize leakage of acoustic wave energy.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: November 14, 2023
    Assignee: GLOBAL COMMUNICATION SEMICONDUCTORS, LLC
    Inventors: Shing-Kuo Wang, Liping Daniel Hou, Yuefei Yang
  • Patent number: 11276764
    Abstract: A device including a semiconductor die, a first contact, a second contact, a third contact, a first passivation layer, a second passivation layer and an interconnect metal. The semiconductor die may include a plurality of semiconductor layers disposed on a GaAs substrate. The first contact may be electrically coupled to a semiconductor emitter layer. The second contact may be electrically coupled to a semiconductor base layer. The third contact may be electrically coupled to a semiconductor sub-collector layer. The first passivation layer may cover one or more of the semiconductor and the contacts. The first passivation layer may comprise an inorganic insulator. The second passivation layer may comprise an inorganic insulator or organic polymer with low dielectric constant deposited on the passivation layer. The interconnect metal may be coupled to the first contact and separated from the first passivation layer by the second passivation layer.
    Type: Grant
    Filed: August 9, 2020
    Date of Patent: March 15, 2022
    Assignee: Global Communication Semiconductors, LLC
    Inventors: Yuefei Yang, Shing-Kuo Wang, Dheeraj Mohata, Liping Daniel Hou
  • Publication number: 20200389150
    Abstract: A single-crystal bulk acoustic wave resonators with better performance and better manufacturability and a process for fabricating the same are described. A low-acoustic-loss layer of one or more single-crystal and/or poly-crystal piezoelectric materials is epitaxially grown and/or physically deposited on a surrogate substrate, followed with the formation of a bottom electrode and then a support structure on a first side of the piezoelectric layer. The surrogate substrate is subsequently removed to expose a second side of the piezoelectric layer that is opposite to the first side. A top electrode is then formed on the second side of the piezoelectric layer, followed by further processes to complete the BAW resonator and filter fabrication using standard wafer processing steps. In some embodiments, the support structure has a cavity or an acoustic mirror adjacent the first electrode layer to minimize leakage of acoustic wave energy.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Inventors: Shing-Kuo Wang, Liping Daniel Hou, Yuefei Yang
  • Publication number: 20200313648
    Abstract: Design and processes are described for fabricating single-crystal bulk acoustic wave resonators with better performance and better manufacturability. A low-acoustic-loss single-crystal piezoelectric layer is epitaxially grown on a substrate, followed with the formation of bottom electrode, metallic cavity frames, and gap filler material on the piezoelectric layer. Matching metallic cavity frames and gap filler material are formed on a second substrate. The two wafers are then bonded together by metal-to-metal bonding of the metallic cavity frames on the first wafer to the matching metallic cavity frame on the second wafer to form a sealed cavity between the bottom electrodes and the second wafer. The first substrate is then removed to expose the piezoelectric layer. This second wafer and the structures thereon are then ready to complete the BAW resonator and filter fabrication using standard wafer processing steps.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Shing-Kuo Wang, Liping Daniel Hou
  • Patent number: 10601391
    Abstract: Devices and processes for preparing devices are described for reducing resonance of spurious waves in a bulk acoustic resonator. A first electrode is coupled to a first side of a piezoelectric layer and a second electrode is coupled to a second side of the piezoelectric layer. The piezoelectric layer is configured to resonate in response to an electrical signal applied between the first electrode and the second electrode. Perforations in the first electrode, the piezoelectric layer and/or the second electrode, and/or posts or beams supporting the second electrode, reduce resonance of spurious waves.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 24, 2020
    Assignee: GLOBAL COMMUNICATION SEMICONDUCTORS, LLC.
    Inventors: Robert B. Stokes, Alvin M. Kong, Liping Daniel Hou, Dae-Jin Hyun, Shing-Kuo Wang
  • Publication number: 20180138885
    Abstract: Devices and processes for preparing devices are described for reducing resonance of spurious waves in a bulk acoustic resonator. A first electrode is coupled to a first side of a piezoelectric layer and a second electrode is coupled to a second side of the piezoelectric layer. The piezoelectric layer is configured to resonate in response to an electrical signal applied between the first electrode and the second electrode. Perforations in the first electrode, the piezoelectric layer and/or the second electrode, and/or posts or beams supporting the second electrode, reduce resonance of spurious waves.
    Type: Application
    Filed: October 20, 2017
    Publication date: May 17, 2018
    Inventors: Robert B. Stokes, Alvin M. Kong, Liping Daniel Hou, Dae-Jin Hyun, Shing-Kuo Wang
  • Patent number: 9865690
    Abstract: A method for fabricating a metal structure for a semiconductor device is disclosed. The method begins with providing a wafer with a current input contact and current output contact. Remaining steps include loading the wafer into a deposition apparatus, depositing a layer of metal onto a predefined metal region, removing the wafer from the deposition apparatus, and performing an ex-situ passivation process. If additional layers are to be deposited and passivated, the steps are repeated until a predetermined number of layers of metal are deposited onto the predefined metal region. The predefined metal region is a gate metal opening if the metal structure is a gate contact for a field effect transistor. The ex-situ passivation process is achievable through oxidation or nitridation of the wafer using either oxygen plasma or a nitrogen plasma, respectively. Alternately, oxidation is also achievable through exposing the wafer to air at an elevated temperature.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: January 9, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Liping Daniel Hou, Chuanxin Lian
  • Publication number: 20130267085
    Abstract: A method for fabricating a metal structure for a semiconductor device is disclosed. The method begins with providing a wafer with a current input contact and current output contact. Remaining steps include loading the wafer into a deposition apparatus, depositing a layer of metal onto a predefined metal region, removing the wafer from the deposition apparatus, and performing an ex-situ passivation process. If additional layers are to be deposited and passivated, the steps are repeated until a predetermined number of layers of metal are deposited onto the predefined metal region. The predefined metal region is a gate metal opening if the metal structure is a gate contact for a field effect transistor. The ex-situ passivation process is achievable through oxidation or nitridation of the wafer using either oxygen plasma or a nitrogen plasma, respectively. Alternately, oxidation is also achievable through exposing the wafer to air at an elevated temperature.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 10, 2013
    Inventors: Liping Daniel Hou, Chuanxin Lian
  • Patent number: D660866
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: May 29, 2012
    Assignee: Target Brands, Inc.
    Inventors: Joe Stewart, Daniel Hou, Emily Wengert, Patricia Korth-McDonnell, Stephen Hopf