Patents by Inventor Daniel I. Amey

Daniel I. Amey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140226347
    Abstract: This invention is directed to bendable circuit substrate structures useful for LED mounting and interconnection.
    Type: Application
    Filed: April 16, 2014
    Publication date: August 14, 2014
    Applicant: E I DU PONT DE NEMOURS AND COMPANY
    Inventors: Daniel I. Amey, Deborah R. Gravely, Michael J. Green, Steven H. White
  • Patent number: 8707551
    Abstract: This invention is directed to bendable circuit substrate structures useful for LED mounting and interconnection.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: April 29, 2014
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Daniel I. Amey, Deborah R. Gravely, Michael J. Green, Steven H. White
  • Publication number: 20130330533
    Abstract: This invention is directed to bendable circuit substrate structures useful for LED mounting and interconnection.
    Type: Application
    Filed: August 13, 2013
    Publication date: December 12, 2013
    Applicant: E.I. du Pont de Nemours and Company
    Inventors: Daniel I. Amey, Deborah R. Gravely, Michael J. Green, Steven H. White
  • Publication number: 20120024579
    Abstract: This invention is directed to bendable circuit substrate structures useful for LED mounting and interconnection.
    Type: Application
    Filed: October 7, 2011
    Publication date: February 2, 2012
    Applicant: E. I. DU PONT DE NEMOURS AND COMPANY
    Inventors: DANIEL I. AMEY, Deborah R. Gravely, Michael J. Green, Steven H. White
  • Patent number: 7902662
    Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively and wherein the first and second electrode of the singulated capacitor is interconnected to the first and second electrode respectively of an external planar capacitor embedded within a printed wiring motherboard.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: March 8, 2011
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Daniel I. Amey, William Borland
  • Publication number: 20100304180
    Abstract: This invention is directed to bendable circuit substrate structures useful for LED mounting and interconnection.
    Type: Application
    Filed: December 3, 2008
    Publication date: December 2, 2010
    Applicant: E.I DU PONT DE NEMOURS AND COMPANY
    Inventors: Daniel I. Amey, Deborah R. Gravely, Michael J. Green, Steven H. White
  • Patent number: 7841075
    Abstract: Provided herein are devices comprising a printed wiring board that comprise, singulated capacitors fabricated from known good, thin-film, fired-on-foil capacitors. Provided are methods of incorporating the singulated capacitors into the build-up layers of a printed wiring board to minimize impedance. The singulated capacitors have a pitch that allows each power and ground terminal of an IC to be directly connected to a power and ground electrode, respectively, of its own singulated capacitor. Using a feedstock of known good, fired-on-foil capacitors allows for improved PWB yield.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: November 30, 2010
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William Borland, Daniel I. Amey, Jr., Karl H. Dietz, Cengiz Ahmet Palanduz, J. Stan Erickson
  • Patent number: 7649361
    Abstract: Making process test capacitors simultaneously with circuit capacitors that are to be embedded into a printed wiring board and firing the test capacitors to result in fired-on-foil test capacitors for the purpose of using the test capacitors as test substitutes for the embedded circuit capacitors to predict whether capacitance, dissipation factor or insulation resistance of the circuit capacitors will fall within acceptable specified ranges prior to and after embedment.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: January 19, 2010
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: William Borland, Saul Ferguson, Diptarka Majumdar, Daniel I. Amey
  • Publication number: 20080236877
    Abstract: A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively and wherein the first and second electrode of the singulated capacitor is interconnected to the first and second electrode respectively of an external planar capacitor embedded within a printed wiring motherboard.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 2, 2008
    Applicant: E. I. DUPONT DE NEMOURS AND COMPANY
    Inventors: Daniel I. Amey, William Borland
  • Publication number: 20080145995
    Abstract: Making process test capacitors simultaneously with circuit capacitors that are to be embedded into a printed wiring board and firing the test capacitors to result in fired-on-foil test capacitors for the purpose of using the test capacitors as test substitutes for the embedded circuit capacitors to predict whether capacitance, dissipation factor or insulation resistance of the circuit capacitors will fall within acceptable specified ranges prior to and after embedment.
    Type: Application
    Filed: December 18, 2006
    Publication date: June 19, 2008
    Applicant: E.I. du Pont de Nemours and Company
    Inventors: William J. Borland, Saul Ferguson, Diptarka Majumdar, Daniel I. Amey
  • Patent number: 5519176
    Abstract: A substrate or a ceramic package for packaging semiconductor chips, which comprises an insulating layer having a signal line on one surface of said insulating layer and a power line or ground line corresponding to said signal line on the other surface of said insulating layer. A well-controlled constant high frequency characteristics, and particularly, characteristic impedance, can be obtained on the signal line without being influenced by the power line or ground line.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: May 21, 1996
    Assignee: Sony Corporation
    Inventors: Thomas W. Goodman, Hiroyuki Fujita, Yoshikazu Murakami, Arthur T. Murphy, Daniel I. Amey