Abstract: A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers.

Abstract: A method of demapping in a receiver including deriving M intermediate soft bit values yj for the I and Q data of the input signal as a function of the spacing in the constellation; and limiting the range of the M values yj. A look-up table index is derived for each of the limited M values yj. A look-up table, having 2N+1 entries for supporting up to N soft bit outputs, is indexed using the derived indices; and K soft bits for each of the M values yj of the I and Q data are outputted.

Abstract: A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers.

Abstract: The present method of initial synchronization of a communication signal includes the steps of symbol boundary search, fractional frequency offset estimation, fractional frequency offset compensation, frame boundary search, integer frequency offset estimation, integer frequency offset compensation, preamble segment ID search and preamble cell ID search. The symbol boundary search includes estimating the boundary of a present data symbol by a correlation index for the present data symbol and the correlation index for the next data symbol. The frame boundary search includes identifying the preamble symbol in the symbols found in the symbol boundary search to determine the frame boundary. The integer frequency offset estimation is derived from the pilot subcarriers of the frame control header of the frame after locating the preamble symbol.

Abstract: The multi-band antenna structure includes a first antenna having a band width about a middle frequency and a second antenna spaced and electrically isolated from the antenna. Ends of the second antenna are shorted to each other and the antenna floats electrically. The first and second antennas are planar and superimposed in parallel planes. At least two layers of dielectric material of a thickness is between the two antennas. A third layer of dielectric material of a third thickness is between the two antennas.

Abstract: A scalar Kalman filter is applied for a Least-Square estimated value Hs at s. The filter has an input for receiving Hs, a filter equation and an out for the corrected estimated value Hsk for the kth variable. The filter equation is Hsk=KgainSn[k] wherein: correction Sn[k]=S+Kn(Hs?S); prediction of the correction S=KaSn[k]; Kalman filter gain Kn=P/(1+P); minimum predication MSE P=Ka2Pn[k]+Kb; minimum MSE Pn[k]=P (1?Kn); and Ka, Kgain and Kb are constants.

Abstract: An amplitude modulation receiver including an antenna for receiving a signal and an input filter connected to the antenna. A variable gain amplifier is connected to the input filter and is responsive to a gain control signal. An A/D converter is connected to the variable gain amplifier and is responsive to a sampling signal and provides a sampled digital signal. A D/A converter receives a demodulated signal and provides an analog output signal. A controller receives and demodulates the sampled digital signal from the A/D converter, generates the gain control signal for the variable gain amplifier, generates the sampling signal for the A/D converter, and provides the demodulated signal to the D/A converter. The demodulation and generation of the gain control signal and the sampling signal are performed in software.

Abstract: The multi-band antenna structure includes a first antenna having a band width about a middle frequency and a second antenna spaced and electrically isolated from the antenna. Ends of the second antenna are shorted to each other and the antenna floats electrically. The first and second antennas are planar and superimposed in parallel planes. At least two layers of dielectric material of a thickness is between the two antennas. A third layer of dielectric material of a third thickness is between the two antennas.

Abstract: An analog TV receiver implementation on DSP allows mobile platforms to view analog TV broadcasting on LCD displays. The analog television receiver includes a demodulator for demodulating a received analog television signal, an analog to digital converter for digitizing the demodulated television signal and a digital signal processor for producing display signals from the digitized television signals. The digital signal processor being programmed to search for a horizontal synchronization signal in the television signal, track the horizontal synchronization signal and search for a vertical synchronization signal in the television signal. Next the processor separates a luminance and a pair of chrominance components of the television signal and demodulates the pair of chrominance components. Red, green and blue values are constructed from the demodulated chrominance components and the luminance components. Display signals are produced from the red, green and blue values.

Abstract: A method of demapping in a receiver including deriving M intermediate soft bit values yj for each of the I and Q data of the input signal as a function of the spacing in the constellation; and limiting the range of the M values yj. A look-up table index is derived for each of the limited M values yj. A look-up table, having 2N+1 entries for supporting up to N soft bit outputs, is indexed using the derived indices; and K soft bits for each of the M values yj of the I and Q data are outputted.

Abstract: A method and apparatus for decoding a coded data stream of bits using an inner decoder, deinterleaver and an outer decoder. The outer decoder first decodes by error correction decoding for r errors per word. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the first decoding are all zeros. If the syndromes of the corrected word of the first decoding are not all zeros, a second decoding is performed by error decoding and erasure for the number of errors reduced by one and the number of erasures increased to two. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the second decoding are all zeros. If the syndromes of the corrected word of the second decoding are not all zeros, the second decoding by correcting and erasure decoding is repeated for the number of errors reduced by one and the number of erasures increased by two for each iteration of the second decoding.

Abstract: The present method of initial synchronization of a communication signal includes the steps of symbol boundary search, fractional frequency offset estimation, fractional frequency offset compensation, frame boundary search, integer frequency offset estimation, integer frequency offset compensation, preamble segment ID search and preamble cell ID search. The symbol boundary search includes estimating the boundary of a present data symbol by a correlation index for the present data symbol and the correlation index for the next data symbol. The frame boundary search includes identifying the preamble symbol in the symbols found in the symbol boundary search to determine the frame boundary. The integer frequency offset estimation is derived from the pilot subcarriers of the frame control header of the frame after locating the preamble symbol.

Abstract: A receiver for orthogonal frequency division multiplexing signals, including art A/D converter for converting receiver analog signals to a digital signal data stream, wherein the digital signal data stream includes symbols separated by guard segments. The receiver also includes an I/Q demodulator for producing a first set of complex I and Q components from the digital signal data stream and a guard segment length detector using the first set of I and Q components. It further includes an extractor for identifying and removing the guard segments of the detected length from the digital signal data stream and an FFT demodulator for demodulating the symbols of the digital signal data stream to produce second sets of complex I and Q components.

Abstract: A receiver for orthogonal frequency division multiplexing signals, including an A/D converter (52) for converting receiver analog signals to a digital signal data stream, wherein the digital signal data stream includes symbols separated by guard segments. The receiver also includes an I/Q demodulator (54) for producing a first set of complex I and Q components from the digital data stream and a guard segment length detector (58) using the first set of I and Q components. It further includes an extractor (62) for extracting and removing the guard segments of the detected length from the digital signal data stream and an FFT demodulator (64) for demodulating the symbols of the digital signal data stream to produce second sets of complex I and Q components.

Abstract: The present invention involves padding the bit sequence in the first interleaver. The present method adds to an end of the bit sequence a sufficient number of padding bits L to permit modulus 16 operation of the bit sequence. After performing the interleaving, L bits are removed from an end of the interleaved sequence. This allows the interleaving to be performed in 16-bit segments simultaneously.

Abstract: A scalar Kalman filter is applied for a Least-Square estimated value Hs at s. The filter has an input for receiving Hs, a filter equation and an out for the corrected estimated value Hsk for the kth variable. The filter equation is Hsk=KgainSn[k] wherein: correction Sn[k]=S+Kn(Hs?S); prediction of the correction S=KaSn[k]; Kalman filter gain Kn=P/(1+P); minimum predication MSE P=Ka2Pn[k]+Kb; minimum MSE Pn[k]=P (1?Kn); and Ka, Kgain and Kb are constants.

Abstract: A receiver includes a controller which receives A/D sampled input signals and shifts the sampled digital signal to compensate for Doppler effect in the input signal prior to demodulation. The controller compensates for a Doppler increased frequency by shifting the sampled digital signal so as to skip a sample period every n samples. This may be achieved by decreasing a cycle of m samples by one sample period every n samples. The controller compensates for a Doppler decreased frequency by shifting the sampled digital signal so as to add a sample period every n samples. This may be achieved by repeating a sample every n samples to shift the sampled digital signal. The compensation is performed in software on a multi-threaded processor.

Abstract: An analog TV receiver implementation on DSP allows mobile platforms to view analog TV broadcasting on LCD displays. The analog television receiver includes a demodulator for demodulating a received analog television signal, an analog to digital converter for digitizing the demodulated television signal and a digital signal processor for producing display signals from the digitized television signals. The digital signal processor being programmed to search for a horizontal synchronization signal in the television signal, track the horizontal synchronization signal and search for a vertical synchronization signal in the television signal. Next the processor separates a luminance and a pair of chrominance components of the television signal and demodulates the pair of chrominance components. Red, green and blue values are constructed from the demodulated chrominance components and the luminance components. Display signals are produced from the red, green and blue values.

Abstract: A radio including a first channel for receiving signals at a first frequency and a second channel for receiving and transmitting signals at a second frequency. A multiplexer connects the first and second channels through an A/D and D/A converter to a digital signal processor. An oscillator is connected to and provides a common sampling frequency to the A/D and D/A converters. The digital signal processor controls the multiplexer and modifies the received digital signals to accommodate for the different carrier frequencies of the channels using the common sampling rate. A frequency synthesizer is connected to the oscillator and provides different frequency signals for the channels. A third channel may be provided for receiving and transmitting signals at a third frequency and is also connected to the multiplexer. The processor is capable of performing communication protocols for at least two of the channels simultaneously.

Abstract: A method and apparatus for decoding a coded data stream of bits using an inner decoder, deinterleaver and an outer decoder. The outer decoder first decodes by error correction decoding for r errors per word. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the first decoding are all zeros. If the syndromes of the corrected word of the first decoding are not all zeros, a second decoding is performed by error decoding and erasure for the number of errors reduced by one and the number of erasures increased to two. The decoding is terminated and a decoded word is outputted if the syndromes of the corrected word of the second decoding are all zeros. If the syndromes of the corrected word of the second decoding are not all zeros, the second decoding by correcting and erasure decoding is repeated for the number of errors reduced by one and the number of erasures increased by two for each iteration of the second decoding.