Abstract: An elliptical exercise apparatus includes a frame, a pair of footpads, and a linkage coupling the footpads to the frame and for guiding the footpads in closed paths when a user's feet apply forces to the footpads. The linkage, which includes a rotatable member having an angular position indicative of the positions of the footpads within their closed paths, responds to input control signals by adjusting length and height dimensions of the closed paths. A control system senses the angular position of the rotatable member, senses the forces the user applies to the footpads, and generates the control signals to increase or decrease the path dimensions when it senses particular combinations of angular position and user forces, thereby permitting the user to control the path dimensions by controlling the forces applied to the footpads.

Abstract: An elliptical exercise apparatus includes a frame, a pair of footpads, and a linkage coupling the footpads to the frame and for guiding the footpads in closed paths when a user's feet apply forces to the footpads. The linkage, which includes a rotatable member having an angular position indicative of the positions of the footpads within their closed paths, responds to input control signals by adjusting length and height dimensions of the closed paths. A control system senses the angular position of the rotatable member, senses the forces the user applies to the footpads, and generates the control signals to increase or decrease the path dimensions when it senses particular combinations of angular position and user forces, thereby permitting the user to control the path dimensions by controlling the forces applied to the footpads.

Abstract: An elliptical exercise apparatus includes a frame, a pair of footpads, and a linkage coupling the footpads to the frame and for guiding the footpads in closed paths when a user's feet apply forces to the footpads. The linkage, which includes a rotatable member having an angular position indicative of the positions of the footpads within their closed paths, responds to input control signals by adjusting length and height dimensions of the closed paths. A control system senses the angular position of the rotatable member, senses the forces the user applies to the footpads, and generates the control signals to increase or decrease the path dimensions when it senses particular combinations of angular position and user forces, thereby permitting the user to control the path dimensions by controlling the forces applied to the footpads.

Abstract: A nursing bottle includes a container having a threaded neck, a flanged nipple seated on the neck and a cap having a central opening through which the nipple extends. A threaded ring on the cap engages the threaded bottle neck with the outer circumferential edge of the nipple's flange compressed between the annular top and the rim of the bottle neck. A small slit in an area of thinned material at the nipple tip opens when the baby nurses and substantially closes when the baby is not nursing. The nipple flange includes a vent hole between its inner and outer circumferential edges, and an annular bead between its inner circumferential edge and the aperture. The annular bead engages the cap top when air pressure within the container is not substantially lower than air pressure external to the container, thereby providing a seal between the aperture and external air.

Abstract: An integrated circuit (IC) tester includes a set of digital and analog channels, each of which may be programmed to carry out a sequence of test activities at pins of an IC under test. The channels are interconnected by a trigger bus, and each channel may be programmed to respond to a detected event during a test by transmitting a particular trigger code to every other channel via the trigger bus. Each channel may be also programmed to respond to a particular trigger code arriving on the trigger bus by branching its sequence of test activities. Thus any channel detecting an event during a test can signal all other channels to immediately terminate a current sequence of test activities and branch to another set of test activities. Such a conditional branch capability enables the tester to automatically perform an "if/then" diagnostic test on an IC in which a test result detected at any point during the test determines the future course of the test.

Abstract: A method of operating an integrated circuit (IC) tester is disclosed in which an IC is repeatedly tested with respect to a limited number of combinations of values of two variable IC operating parameters (X and Y) to determine the boundary of a two-dimensional range of combinations of values of the X and Y parameters for which the IC passes a test. After finding a combination of X and Y parameter values on the boundary, each combination of parameter values to be tested thereafter is selected by altering either the X or Y parameter value, with the decision based on whether the IC passed the last test and on the manner in which a last tested combination of X and Y parameter values was selected.

Abstract: A digitizer can be programmed to digitize an ANALOG signal with a complex frequency pattern determined in response to set of trigger signals. The digitizer includes an addressable packet memory storing a set of data packets and produces one of its stored data packets as output when addressed. The output data packet includes both PERIOD and MODE data fields. The digitizer also incudes an analog-to-digital converter for digitizing the ANALOG signal at the frequency controlled by the PERIOD data output of the packet memory. The MODE data output of the packet memory tells a trigger logic circuit how to choose a next packet memory address and selects one of the trigger signals to tell the trigger logic circuit when to change the packet memory address so as to alter the digitizing frequency.

Abstract: A network switch routes data transmissions between uniquely addressed network stations connected to input and output ports of the switch. The switch includes a hierarchical address translation system for relating network addresses of stations to receive incoming transmission to the switch ports to which they are connected. The translation system includes a central translation unit having a memory for storing a mapping entry for each network station, the entry mapping the station's network address to its switch port. The system also includes a local translation unit in each input port. Each local translation unit contains a local cache memory for storing a smaller subset of the mapping entries stored by the central translation unit. When a data transmission arrives at an input port directed to a network address, the input port looks for an entry in its cache memory mapping that network address to an output port.

Abstract: A system for distributing synchronized clock signals to spatially distributed circuits includes a pair of transmission lines, each extending between first and second sites. The transmission lines are interconnected at the second site so that an outgoing clock signal traveling on the first transmission line from the first site to the second site returns to the first site on the second transmission line. Spatially distributed deskewing circuits tap the signal transmission lines between the first and second sites. A first delay circuit in each deskewing circuit detects the outgoing clock signal on the first transmission line and produces a local clock signal that lags the outgoing clock signal by an adjustable delay time. A similar second delay circuit in each deskewing circuit delays the local clock signal by a similar adjustable delay time to produce a local reference signal.

Abstract: A system for distributing synchronous clock signals includes a set of spatially distributed deskewing stages. Each stage includes matching adjustable first and second delay circuits and a phase lock loop controller. Matching pairs of transmission lines interconnect successive stages of the set. One transmission line of each pair connects the output of the first delay circuit of each stage to the input of the first delay circuit of a next stage of the set. The other transmission line of the pair connects the input of the second delay circuit of the stage to the input of the first delay circuit of the next stage. When the first delay circuit of the first stage of the set receives an input reference clock signal, that reference clock signal propagates through all the first delay circuits of each stage in succession. Whenever the input reference clock signal reaches a stage, it also travels back to the second delay circuit of the preceding stage.

Abstract: A beverage containing sugar is carbonated by first placing the beverage and a small amount of yeast in a bottle. A small paper disk impregnated or coated with a yeast-killing sterilizing agent such as sodium metabisulfite is attached to the underside of a bottle cap. The bottle is then sealed with the cap and stored in an upright position with the bottle cap holding the disk above the beverage. After the yeast has fermented a sufficient amount of the sugar to adequately carbonate the beverage, the bottle is shaken for a time to allow the beverage to rinse the yeast-killing agent from the disk. As the agent mixes with the beverage, it kills the yeast in the bottle, thereby terminating fermentation of the sugar.

Abstract: A timing signal generator includes a voltage controlled oscillator (VCO), a logic circuit, N set circuits and N reset circuits and a bistable latch circuit. The VCO produces a set of N reference signals frequency locked to a reference clock signal and distributed in phase so as to evenly resolve the reference clock period into N intervals. The logic circuit asserts ones of N set signals and N reset signals selected by input control words. Each set circuit receives one of the N set signals and one of the N reference signals and briefly couples an output node to high logic level source in response to a leading edge of the received reference signal when its received set signal is asserted. Each reset circuit receives one of the N reset signals and one of the N reference signals and briefly couples the output node to low logic level source in response to a leading edge of its received reference signal when it reset signal is asserted.