Patents by Inventor Daniel J. Chu
Daniel J. Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947890Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).Type: GrantFiled: May 8, 2020Date of Patent: April 2, 2024Assignee: SanDisk Technologies LLCInventors: Cheng-Chung Chu, Janet George, Daniel J. Linnen, Ashish Ghai
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Publication number: 20240081991Abstract: Delivery systems for expandable and stented implants include adjustable tensioning members that control the expansion of the implant along the length of the implant. The tensioning members are wound onto one or more rotors located on the distal segment of the delivery system, which are rotated to unwind the tensioning members and incrementally expand the implant. Positioning mechanisms are also provided to adjust the position and orientation of the implant during delivery.Type: ApplicationFiled: February 10, 2022Publication date: March 14, 2024Inventors: Daniel T. Wallace, Peter W. Gregg, Jeremy J. Boyette, Evelyn N. Haynes, Spencer C. Noe, Diana L. Chu
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Patent number: 10325652Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.Type: GrantFiled: August 29, 2017Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: Daniel J. Chu, Raymond W. Zeng, Doyle Rivers
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Patent number: 10037799Abstract: Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.Type: GrantFiled: June 28, 2016Date of Patent: July 31, 2018Assignee: Intel CorporationInventor: Daniel J. Chu
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Publication number: 20180068720Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.Type: ApplicationFiled: August 29, 2017Publication date: March 8, 2018Applicant: Intel CorporationInventors: Daniel J. Chu, Raymond W. Zeng, Doyle Rivers
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Patent number: 9747977Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.Type: GrantFiled: March 14, 2013Date of Patent: August 29, 2017Assignee: INTEL CORPORATIONInventors: Daniel J. Chu, Raymond W. Zeng, Doyle Rivers
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Publication number: 20170025171Abstract: Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.Type: ApplicationFiled: June 28, 2016Publication date: January 26, 2017Applicant: Intel CorporationInventor: Daniel J. Chu
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Patent number: 9406378Abstract: Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.Type: GrantFiled: December 4, 2014Date of Patent: August 2, 2016Assignee: Intel CorporationInventor: Daniel J. Chu
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Patent number: 9286975Abstract: The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.Type: GrantFiled: March 11, 2014Date of Patent: March 15, 2016Assignee: Intel CorporationInventors: Daniel J. Chu, Kiran Pangal, Nathan R. Franklin, Prashant S. Damle, Hu Chaohong
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Publication number: 20150262661Abstract: The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.Type: ApplicationFiled: March 11, 2014Publication date: September 17, 2015Applicant: Intel CorporationInventors: DANIEL J. CHU, KIRAN PANGAL, NATHAN R. FRANKLIN, PRASHANT S. DAMLE, HU CHAOHONG
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Publication number: 20150085570Abstract: Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.Type: ApplicationFiled: December 4, 2014Publication date: March 26, 2015Inventor: Daniel J. Chu
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Patent number: 8913425Abstract: Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.Type: GrantFiled: March 12, 2013Date of Patent: December 16, 2014Assignee: Intel CorporationInventor: Daniel J. Chu
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Publication number: 20140269043Abstract: Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Inventor: DANIEL J. CHU
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Publication number: 20140269045Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Daniel J. Chu, Raymond W. Zeng, Doyle Rivers
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Patent number: 8630107Abstract: A multi-die memory package may have separate chip enable inputs for the respective memory dice. Individual chip enable inputs may be separated by other chip connections such as power and ground. The memory dice may include multiple chip enable inputs to allow easy wire bonding of the individual chip enable inputs to a die without requiring any jumpers within the package. Circuitry may be included so that undriven chip enable inputs are masked and driven chip enable inputs may be propagated to the memory die to enable memory accesses while a single chip enable input is only connected to the capacitance of a single bonding pad.Type: GrantFiled: August 9, 2012Date of Patent: January 14, 2014Assignee: Intel CorporationInventor: Daniel J. Chu
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Publication number: 20130010517Abstract: A multi-die memory package may have separate chip enable inputs for the respective memory dice. Individual chip enable inputs may be separated by other chip connections such as power and ground. The memory dice may include multiple chip enable inputs to allow easy wire bonding of the individual chip enable inputs to a die without requiring any jumpers within the package. Circuitry may be included so that undriven chip enable inputs are masked and driven chip enable inputs may be propagated to the memory die to enable memory accesses while a single chip enable input is only connected to the capacitance of a single bonding pad.Type: ApplicationFiled: August 9, 2012Publication date: January 10, 2013Inventor: Daniel J. Chu
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Patent number: 7317346Abstract: One or more MOS devices may be used as a bias selecting circuit to pass a bias voltage from a bias generator to a level shifting circuit.Type: GrantFiled: March 11, 2005Date of Patent: January 8, 2008Assignee: Intel CorporationInventors: Daniel J. Chu, Raymond W. Zeng
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Patent number: 7116151Abstract: Methods and apparatuses associated with stepping down a high voltage in a high voltage switch. An additional transistor may be coupled to a switching transistor, and the additional transistor biased to a voltage level in between the high voltage to be switched and a switch reference voltage. When the switch is off, the high voltage may thus be spread across multiple devices to prevent a voltage from the gate to the drain to exceed a threshold associated with gate-aided breakdown of the drain-to-substrate channel-side pn-junction.Type: GrantFiled: June 30, 2004Date of Patent: October 3, 2006Assignee: Intel CorporationInventors: Gerald J. Barkley, Daniel J. Chu