Abstract: A high-speed binary divider is provided which produces two quotient bits per processor cycle using two carry-save adders in a nonrestoring division mode with a delayed sign logic circuit selecting the adder having the required adder result for the current partial remainder.

Abstract: A shift network is provided which may operate on one full width operand or on two one-half width operands, by splitting the shift network in the middle. The shift network in the present embodiment for 96 bit full width operands is constructed in four ranks so that the first rank shifts operand bits 0, 1, 2 or 3 bit positions, the second rank shifts operand bits 0 or 4 bit positions, the third rank shifts operand bits 0, 32, 64 or 96 bit positions, and the fourth rank shifts operand bits 0, 8, 16 or 24 bit positions, all shifts dependent upon the input shift count.The shift network is responsive to two independent shift counts and a control signal specifying the half width mode when it is desired to split the network. Each rank of the shift network is divided into an upper half and a lower half. Special logic circuits are provided to extend the sign bit for the lower half operand into the lower half of each rank when operating in the two operand mode.