Abstract: Systems and methods of the present disclosure include at least one building component detection sensor device configured to be deployed within (or proximate to) a building comprised of a plurality of building components. The at least one building component detection sensor device is configured to detect data relating to at least one building component of the plurality of building components. In addition, a building component property determination system includes a processor configured to execute instructions stored in memory to determine one or more properties of the at least one building component based at least in part on the data detected by the at least one building component detection sensor device.

Abstract: A processor in accordance with the present invention includes memory that stores test data and control data. The processor also includes a test application that transmits the test data and the control data from the processor's memory to a test access port of the processor. The test access port then utilizes the test data and the control data to capture state data that defines at least one state of the processor while the processor is executing. This test data may be analyzed via conventional techniques to detect and isolate errors in the execution of the processor.

Abstract: A method and system for performing in-place insertion of interconnect repeaters in an integrated circuit is presented. The integrated circuit comprises a silicon layer and at least one interconnect layer layered over said silicon layer. Metal tracks are reserved on each of the interconnect layers in predefined repeater areas. The interconnects are then routed to pass over the pre-defined repeater areas. For each interconnect, a set of optimal constrained repeater locations are calculated, as defined by the optimal number and locations of repeaters along the interconnect route and as constrained by a set of legal repeater locations associated with the interconnect and which will result in acceptable timing criteria. For each calculated optimal constrained repeater location, a repeater is stitched in-place through the reserved metal tracks of the intervening layers.

Abstract: A system for testing a microprocessor having a core execution unit, an internal memory, and a data port may comprise a tester having a data port which is connected to the microprocessor data port. A test vector generator program is transferred from the tester to the internal memory of the microprocessor for testing the microprocessor when the test vector generator program is executed by the core execution unit. The test vector generator program generates test vectors which are also stored in the internal memory, and which may then be executed by the core execution unit.

Abstract: A system for testing a microprocessor having a core execution unit, an internal memory, and a data port may comprise a tester having a data port which is connected to the microprocessor data port. A test vector generator program is transferred from the tester to the internal memory of the microprocessor for testing the microprocessor when the test vector generator program is executed by the core execution unit. The test vector generator program generates test vectors which are also stored in the internal memory, and which may then be executed by the core execution unit.

Abstract: A unified bi-directional LFSR is fabricated from latches having dual (Forward and Reverse) inputs. Each such latch accepts its inputs upon receipt of a clock signal that is respectively associated with the forward or reverse direction. The appropriate collection of XOR gates exists between latch outputs and the inputs associated with a forward clock signal, so as to produce the forward sequence. Likewise, another appropriate collection of XOR gates exists between the latch outputs and the inputs associated with the reverse clock signal. To produce a "reverse" LFSR corresponding to the polynomial that is the reciprocal of the polynomial for the "forward" LFSR, the latches of the reciprocal (reverse direction) LFSR are construed as being numbered in the opposite order. That is, a single set of latches (register) has both a forward linear feedback network and a reverse linear feedback network.

Abstract: A parity generation circuit for an internal cache memory of a computer processor. The parity generation circuit generates parity for both reading and writing during execution of a single processor instruction. The parity generation circuit saves processor circuitry by sharing one parity logic tree for both reading and writing. During one clock phase, a multiplexer routes data to the memory through the parity logic tree and a demultiplexer routes parity from the parity logic tree to the memory. During a second clock phase, the multiplexer routes data from the memory through the parity logic tree and the demultiplexer routes parity from the parity logic tree to the processor.