Patents by Inventor Daniel J. Dolan

Daniel J. Dolan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9430148
    Abstract: A method is provided, for example, to implement multiplexed communication between a controller and a preamplifier in a storage device. For example, multiplexed communication is implemented by controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal, and concurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: August 30, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ross S. Wilson, David W. Kelly, Daniel J. Dolan, Richard Rauschmayer
  • Patent number: 9343103
    Abstract: A method is provided to enable communication between a controller and a preamplifier in a storage device. For example, the method includes implementing a serial port which is configured to transmit digital signals between the controller and the preamplifier over a single bidirectional serial data line. The serial port is controlled to selectively transmit digital signals over the bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: May 17, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ross S. Wilson, Daniel J. Dolan, David W. Kelly, Richard Rauschmayer
  • Patent number: 9281005
    Abstract: A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: March 8, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ross S. Wilson, David W. Kelly, Daniel J. Dolan, Richard Rauschmayer
  • Publication number: 20160012846
    Abstract: A method is provided to enable communication between a controller and a preamplifier in a storage device. For example, the method includes implementing a serial port which is configured to transmit digital signals between the controller and the preamplifier over a single bidirectional serial data line. The serial port is controlled to selectively transmit digital signals over the bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 14, 2016
    Inventors: Ross S. Wilson, Daniel J. Dolan, David W. Kelly, Richard Rauschmayer
  • Publication number: 20150318030
    Abstract: A method is provided, for example, to implement multiplexed communication between a controller and a preamplifier in a storage device. For example, multiplexed communication is implemented by controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal, and concurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus.
    Type: Application
    Filed: May 1, 2014
    Publication date: November 5, 2015
    Applicant: LSI Corporation
    Inventors: Ross S. Wilson, David W. Kelly, Daniel J. Dolan, Richard Rauschmayer
  • Publication number: 20150318014
    Abstract: A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation.
    Type: Application
    Filed: May 1, 2014
    Publication date: November 5, 2015
    Applicant: LSI Corporation
    Inventors: Ross S. Wilson, David W. Kelly, Daniel J. Dolan, Richard Rauschmayer
  • Patent number: 8730608
    Abstract: A read/write head for reducing flying height in a disk drive apparatus includes a write transducer for storing data on a storage medium, a read transducer for reading data from the storage medium, and read and write heater elements configured so that during read/write operations, heat dissipated in the read heater element is greater than heat dissipated in the write heater element. A control pad in the head receives current supplied to the read and write heater elements during read and write operations. During the write operation, protrusion of the read/write head attributable to the write transducer and the write heater element is greater than a protrusion of the head attributable to the read heater element. During the read operation, protrusion of the read/write head attributable to the read heater element and the read transducer is greater than a protrusion of the head attributable to the write heater element.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 20, 2014
    Assignee: LSI Corporation
    Inventors: Thomas C. Van Eaton, Jun Oie, Daniel J. Dolan, Jr.
  • Publication number: 20140032814
    Abstract: A hybrid storage device comprises at least one storage disk, a disk controller configured to control writing of data to and reading of data from the storage disk, a non-volatile electronic memory, and a bridge device coupled between the disk controller and the non-volatile electronic memory. The disk controller comprises a plurality of high-speed serial interfaces. In one embodiment, the high-speed serial interfaces include a first high-speed serial interface configured to interface the disk controller to a host device, and a second high-speed serial interface configured to interface the disk controller to the non-volatile memory via the bridge device. The non-volatile memory may comprise a flash memory, and the bridge device may comprise a flash controller. The disk controller may be implemented in the form of an SOC integrated circuit that is operative in a plurality of modes including a hybrid mode of operation and an enterprise mode of operation.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Applicant: LSI Corporation
    Inventors: Daniel S. Fisher, Jun Oie, Jeffrey J. Holm, Philip G. Brace, Daniel J. Dolan, JR.
  • Publication number: 20130043655
    Abstract: A simulated game of Basketball that is played using an existing Basketball hoop, Basketball and specialized marked deck of cards comprising of multiple cards marked 1 2 3 4 5 6 7 8 and Wild Card. Also, the game incorporates eight bean bags numbered 1 2 3 4 5 6 7 and 8. The game is played using an existing Basketball hoop and Basketball. The scoring is determined by the points on the specialized deck of cards that corresponds to the bean bags the player shoots the ball from. The player with the highest score at the end of the game wins.
    Type: Application
    Filed: August 19, 2011
    Publication date: February 21, 2013
    Inventor: Daniel J. Dolan
  • Patent number: 7692887
    Abstract: An apparatus and method for determining a head parameter value (e.g., head resistance) of a resistive head. A test head current is supplied to the head during a head parameter measurement interval using the same current sources that supply a bias current to the head during an operating (read operation) interval. The determined head parameter value is latched for use in setting the control loop gain for a control loop that controls the current sources during the operating interval.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: April 6, 2010
    Assignee: Agere Systems Inc.
    Inventors: Daniel J. Dolan, Jr., Hao Fang, Jeffrey A. Gleason, Ross S. Wilson
  • Patent number: 7642617
    Abstract: An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: January 5, 2010
    Assignee: Agere Systems Inc.
    Inventors: Alan Sangone Chen, Daniel J. Dolan, Jr., David W. Kelly, Daniel Charles Kerr, Stephen C. Kuehne
  • Patent number: 7595951
    Abstract: A (e.g., hard-disk drive (HD)) system supports reader standby mode and/or writer standby mode. For reader standby mode, reader circuitry in the system's preamplifier is transitioned to a low-power mode during write operations. To provide quick transition from write mode to read mode, the reader circuitry is transitioned to pre-read mode before the end of the write operation. For writer standby mode, the preamplifier's writer circuitry is transitioned to a low-power mode during read operations. To provide quick transition from read mode to write mode, the writer circuitry is transitioned to a pre-write mode before the end of the read operation. The availability of a reader standby mode during write operations and a writer standby mode during read operations reduces power consumption as compared to HD systems that leave the reader circuitry in pre-read mode throughout each write operation and the writer circuitry in pre-write mode throughout each read operation.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: September 29, 2009
    Assignee: Agere Systems Inc.
    Inventors: Daniel J. Dolan, David W. Kelly, Stephen C. Kuehne, Nathan M. Rudd, Ross S. Wilson
  • Publication number: 20080062551
    Abstract: An apparatus and method for determining a head parameter value (e.g., head resistance) of a resistive head. A test head current is supplied to the head during a head parameter measurement interval using the same current sources that supply a bias current to the head during an operating (read operation) interval. The determined head parameter value is latched for use in setting the control loop gain for a control loop that controls the current sources during the operating interval.
    Type: Application
    Filed: September 13, 2006
    Publication date: March 13, 2008
    Inventors: Daniel J. Dolan, Hao Fang, Jeffrey A. Gleason, Ross S. Wilson
  • Publication number: 20070279785
    Abstract: A (e.g., hard-disk drive (HD)) system supports reader standby mode and/or writer standby mode. For reader standby mode, reader circuitry in the system's preamplifier is transitioned to a low-power mode during write operations. To provide quick transition from write mode to read mode, the reader circuitry is transitioned to pre-read mode before the end of the write operation. For writer standby mode, the preamplifier's writer circuitry is transitioned to a low-power mode during read operations. To provide quick transition from read mode to write mode, the writer circuitry is transitioned to a pre-write mode before the end of the read operation. The availability of a reader standby mode during write operations and a writer standby mode during read operations reduces power consumption as compared to HD systems that leave the reader circuitry in pre-read mode throughout each write operation and the writer circuitry in pre-write mode throughout each read operation.
    Type: Application
    Filed: June 2, 2006
    Publication date: December 6, 2007
    Inventors: Daniel J. Dolan, David W. Kelly, Stephen C. Kuehne, Nathan M. Rudd, Ross S. Wilson
  • Patent number: 7119977
    Abstract: User data is read from a medium having servo data and user data encoded thereon. The user data is read with a read/write head that is operable in a write mode and a read mode. Servo data is read in a time window following a transition from write mode to read mode, with a frequency passband that has a first low frequency corner. User data is read from the medium after expiration of the time window, with a frequency passband that has a second low frequency corner that is lower than the first low frequency corner.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: October 10, 2006
    Assignee: Agere Systems Inc.
    Inventors: Daniel J. Dolan, Jr., James P. Howley, Zachary Keirn, German Feyh, Michael P. Straub
  • Patent number: 6317862
    Abstract: A preamplifier chip for a disk drive is modular in layout. Twelve head cells for the preamplifier chip are not lined along the periphery of the chip, but rather are disposed in an array including four rows of three head cells each. The rows are all directed perpendicular to the side with control connection pads. The preferred embodiment allows for a smaller preamplifier chip through increasing the density of head cells on the chip relative to the periphery of the chip usable for head cell connection. The array spaces write portions of the head cells in four spaced lines, minimizing problems associated with heat build up. Spacing between rows of the array can be determined to take maximum advantage of lead pitch on the flex circuit. Modification of the design to a chip for eight or four channels is possible with minimal changes to the design, and minimal reworking of the common circuitry.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: November 13, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Daniel J. Dolan, Jr., Scott K. Glenna, Charles P. Jents
  • Patent number: 6039449
    Abstract: A temporary snap-in, hold-down, clip includes two sets of snap-fit fingers at opposite ends of a central sleeve for the purposes of temporarily holding a mirror housing to a vehicle body panel during the vehicle assembly process. One set of snap-fit fingers engages the mirror housing and an opposite set of fingers on the clip engages the inside edge of the vehicle body panel hole which normally receives an electrical wiring tail from the mirror assembly. The locking surfaces of barb-like heads on the two sets of fingers are designed so that the clip is more securely held to the mirror housing than to the body panel. A cylindrical sleeve portion of the clip projects outwardly and extends past the mirror housing gasket interposed between the housing and the body panel. The wiring tail passes through the sleeve unless the gasket is protected from the wiring tail as the wiring tail is pulled to the side by the installer.
    Type: Grant
    Filed: September 23, 1998
    Date of Patent: March 21, 2000
    Assignee: Delbar Products, Inc.
    Inventors: Daniel J. Dolan, John S. McPherson