Abstract: A threshold voltage compensation method and circuit compensates a bias voltage applied to a transistor gate to account for variations in the transistors threshold voltage. In one embodiment, a logic stack includes three transistors in series between a high voltage source and ground with a higt voltage output between the first and second transistor and a full swing output between the second transistor and the third transistor. A bias voltage is applied to the gate of the second transistor to provide a minimum voltage level for the high voltage output. As the threshold voltage of the second transistor varies, the bias voltage is adjusted to compensate for the threshold voltage level variance and maintain the minimum voltage level for the higt voltage output.

Abstract: A semiconductor component is described which directs transmission of data. The component comprises of a decoder device coupled to said first memory device capable of decoding an address of said data in said first format using said stored address in said first memory device. The component also comprises a translator device coupled to said second memory device capable of transmitting said address of said data in said second format corresponding to said address of said data in said first format, wherein the second format contains the same amount of information as the first format.