Abstract: The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of "hot bits" existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the same time that the branch will be executed.

Abstract: This processor is a single chip implementation of an architecture that is designed to expeditiously handle certain tasks commonly associated with signal processing. Sequential multiply and accumulate operations, in particular, can be accomplished quite efficiently. The processor is pipelined in two areas. Instructions are passed through a three phase pipeline and consist of fetch, decode and execute, while the multiplier utilizes a two phase pipeline. The data flow is parallel and of 16-bit width throughout. The instruction store is maintained separately from the data store and provisions are included for having the processor enabled to read and write its own instruction store. Some parallel or compound instructions are implemented to permit transfer actions such as storage or I/O to or from instruction registers to occur concurrently with a compute action in different segments of the data flow. The arithmetic capabilities of the processor include both the separate multiplier and a full arithmetic logic unit.

Abstract: This improved speech signal Block Coded PCM (BCPCM) system reduces the number of bits allocated to transmitting the scale factor, thereby releasing bits for allocation to coding samples in the associated block of samples. The scale factor (c) is calculated for every 16 millisecond block of samples. However, the scale factor will be transmitted only once per 32 millisecond block if there is no significant difference between the two sequential values. The original speech signal is split into 16 frequency subbands, each subband initials sampled and 12-bit coded, then requantized in BCPCM at dynamically variable bit rates depending on the scale factor transmission rate.

Abstract: The improved multiplexer described herein uses split band encoding across a plurality of input ports to increase the statistical advantage for compression gains but does not require a large number of input ports to achieve its advantage.

Abstract: A voice signal is transmitted digitally at reduced bit rate by use of data compression. The original frequency components of a telephone band width of the voice signal sampled at 8 KHz and quantized with 12 bits are transformed into three parameters: SIGNAL data representing adaptive quantization for lower frequency (300-800 Hz) sub-bands; COEF data representing pre-emphasized parcor type coefficients for the higher frequency (800-3000 Hz) band; and, ENERGY data representing higher frequency short term energy level. The three parameters are multiplexed for transmission in binary-code form, thereby representing a recoding of the original binary-coded voice signals.

Abstract: This is a block quantizer which converts a given block of samples into an optimum sequence of numbers describing the sampled signal with minimum distortion due to the quantizing process.The quantizer self-adjusts the basic parameters, i.e., quantizing step Q, d.c. level C and the sequence of numbers fn, describing the signal for each block of samples for a minimal Mean Squared Error.