Patents by Inventor Daniel J. Ewing
Daniel J. Ewing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9881849Abstract: An integrated circuit and method of forming the integrated circuit, including the steps of forming channels partially into a thickness of a semiconductor layer or through the thickness of the semiconductor layer and partially through a thickness of a substrate layer on which the semiconductor layer was formed. The method may then include underfilling or overfilling the channels with diamond. If underfilled, a remainder of the channels may be filled in with nucleation buffer layers or additional semiconductor material. If overfilled, the diamond may be selectively polished down to form a planar surface with the semiconductor layer. Next, the method may include forming an active device layer over the semiconductor material and diamond. The method may also include thinning the substrate layer down to the diamond and then placing a heat sink in physical contact with the diamond in the channel.Type: GrantFiled: January 5, 2017Date of Patent: January 30, 2018Assignee: Honeywell Federal Manufacturing & Technologies, LLCInventors: Kyle W. Maples, Daniel J. Ewing
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Patent number: 9728483Abstract: An integrated circuit and method of forming the integrated circuit, including the steps of forming channels partially into a thickness of a semiconductor layer or through the thickness of the semiconductor layer and partially through a thickness of a substrate layer on which the semiconductor layer was formed. The method may then include underfilling or overfilling the channels with diamond. If underfilled, a remainder of the channels may be filled in with nucleation buffer layers or additional semiconductor material. If overfilled, the diamond may be selectively polished down to form a planar surface with the semiconductor layer. Next, the method may include forming an active device layer over the semiconductor material and diamond. The method may also include thinning the substrate layer down to the diamond and then placing a heat sink in physical contact with the diamond in the channel.Type: GrantFiled: December 9, 2015Date of Patent: August 8, 2017Assignee: Honeywell Federal Manufacturing & Technologies, LLCInventors: Kyle W. Maples, Daniel J. Ewing
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Publication number: 20170170094Abstract: An integrated circuit and method of forming the integrated circuit, including the steps of forming channels partially into a thickness of a semiconductor layer or through the thickness of the semiconductor layer and partially through a thickness of a substrate layer on which the semiconductor layer was formed. The method may then include underfilling or overfilling the channels with diamond. If underfilled, a remainder of the channels may be filled in with nucleation buffer layers or additional semiconductor material. If overfilled, the diamond may be selectively polished down to form a planar surface with the semiconductor layer. Next, the method may include forming an active device layer over the semiconductor material and diamond. The method may also include thinning the substrate layer down to the diamond and then placing a heat sink in physical contact with the diamond in the channel.Type: ApplicationFiled: January 5, 2017Publication date: June 15, 2017Applicant: HONEYWELL FEDERAL MANUFACTRING & TECHNOLOGIES, LLCInventors: Kyle W. Maples, Daniel J. Ewing
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Publication number: 20170170093Abstract: An integrated circuit and method of forming the integrated circuit, including the steps of forming channels partially into a thickness of a semiconductor layer or through the thickness of the semiconductor layer and partially through a thickness of a substrate layer on which the semiconductor layer was formed. The method may then include underfilling or overfilling the channels with diamond. If underfilled, a remainder of the channels may be filled in with nucleation buffer layers or additional semiconductor material. If overfilled, the diamond may be selectively polished down to form a planar surface with the semiconductor layer. Next, the method may include forming an active device layer over the semiconductor material and diamond. The method may also include thinning the substrate layer down to the diamond and then placing a heat sink in physical contact with the diamond in the channel.Type: ApplicationFiled: December 9, 2015Publication date: June 15, 2017Applicant: HONEYWELL FEDERAL MANUFACTURING & TECHNOLOGIES, LLCInventors: KYLE W. MAPLES, DANIEL J. EWING
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Patent number: 9646259Abstract: A Josephson junction (JJ) quantum bit (qubits) arranged on a substrate is provided. In one embodiment, each qubit comprises a dielectric layer, a superconductor base layer portion underlying the dielectric layer and a first dielectric diffused region adjacent a dielectric layer/superconductor base layer portion junction. The qubit further comprise a superconductor mesa layer portion overlying the dielectric layer and having a second dielectric diffused region adjacent a dielectric layer/superconductor mesa layer portion junction, the first and second dielectric diffused regions mitigating further diffusion from other semiconductor processes on the plurality of qubits.Type: GrantFiled: August 15, 2014Date of Patent: May 9, 2017Assignee: Northrop Grumman Systems CorporationInventors: Patrick B. Shea, Erica C. Folk, Daniel J. Ewing, John J. Talvacchio
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Patent number: 9355362Abstract: Methods are provided of forming a Josephson junction (JJ) quantum bit (qubit). In one embodiment, the method comprises forming a JJ trilayer on a substrate. The JJ trilayer is comprised of a dielectric layer sandwiched between a bottom superconductor material layer and a top superconductor material layer. The method further comprises performing a thermal hardening process on the JJ trilayer to control diffusion of the dielectric layer into the bottom superconductor material layer and the top superconductor material layer, and etching openings in the JJ trilayer to form one or more JJ qubits.Type: GrantFiled: November 11, 2011Date of Patent: May 31, 2016Assignee: Northrop Grumman Systems CorporationInventors: Patrick B. Shea, Erica C. Folk, Daniel J. Ewing, John J. Talvacchio
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Publication number: 20140357493Abstract: A Josephson junction (JJ) quantum bit (qubits) arranged on a substrate is provided. In one embodiment, each qubit comprises a dielectric layer, a superconductor base layer portion underlying the dielectric layer and a first dielectric diffused region adjacent a dielectric layer/superconductor base layer portion junction. The qubit further comprise a superconductor mesa layer portion overlying the dielectric layer and having a second dielectric diffused region adjacent a dielectric layer/superconductor mesa layer portion junction, the first and second dielectric diffused regions mitigating further diffusion from other semiconductor processes on the plurality of qubits.Type: ApplicationFiled: August 15, 2014Publication date: December 4, 2014Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: PATRICK B. SHEA, ERICA C. FOLK, DANIEL J. EWING, JOHN J. TALVACCHIO
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Publication number: 20130119351Abstract: Methods are provided of forming a Josephson junction (JJ) quantum bit (qubit). In one embodiment, the method comprises forming a JJ trilayer on a substrate. The JJ trilayer is comprised of a dielectric layer sandwiched between a bottom superconductor material layer and a top superconductor material layer. The method further comprises performing a thermal hardening process on the JJ trilayer to control diffusion of the dielectric layer into the bottom superconductor material layer and the top superconductor material layer, and etching openings in the JJ trilayer to form one or more JJ qubits.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Inventors: Patrick B. Shea, Erica C. Folk, Daniel J. Ewing, John J. Talvacchio
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Patent number: 8314016Abstract: A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer.Type: GrantFiled: June 19, 2009Date of Patent: November 20, 2012Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Tsvetanka S. Zheleva, Pankaj B. Shah, Michael A. Derenge, Daniel J. Ewing
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Publication number: 20100171124Abstract: A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer.Type: ApplicationFiled: June 19, 2009Publication date: July 8, 2010Applicant: The United States of America as represented by the Secretary of the ArmyInventors: Tsvetanka S. Zheleva, Pankaj B. Shah, Michael A. Derenge, Daniel J. Ewing