Abstract: A process of fabricating a transistor employs a relatively thicker sacrificial nitride layer that reduces the time and cost associated with chemical-mechanical polish (CMP) processes by reducing the topography associated with the transistor. The process includes forming the gate oxide region and a field oxide region on a substrate. A polysilicon layer is formed on the gate oxide region and the field oxide region. A sacrificial nitride layer is formed on the polysilicon layer, wherein the sacrificial nitride layer has a thickness approximately equal to or greater than a thickness of the gate oxide region. A polysilicon gate is formed by selectively removing portions of the polysilicon layer and the sacrificial layer to expose a portion of the gate oxide region adjacent to the polysilicon gate. Source/drain regions are formed adjacent to the polysilicon gate using lightly-doped drain (LDD) implantation. A spacer layer is formed over the polysilicon gate and source/drain regions.

Abstract: A process of fabricating a transistor employs a relatively thicker sacrificial nitride layer that reduces the time and cost associated with chemical-mechanical polish (CMP) processes by reducing the topography associated with the transistor. The process includes forming the gate oxide region and a field oxide region on a substrate. A polysilicon layer is formed on the gate oxide region and the field oxide region. A sacrificial nitride layer is formed on the polysilicon layer, wherein the sacrificial nitride layer has a thickness approximately equal to or greater than a thickness of the gate oxide region. A polysilicon gate is formed by selectively removing portions of the polysilicon layer and the sacrificial layer to expose a portion of the gate oxide region adjacent to the polysilicon gate. Source/drain regions are formed adjacent to the polysilicon gate using lightly-doped drain (LDD) implantation. A spacer layer is formed over the polysilicon gate and source/drain regions.

Abstract: A method of forming a semiconductor device on a substrate. The method includes forming a first epitaxial layer on the substrate. Next, a selected impurity is introduced to a surface of the first epitaxial layer. A second epitaxial layer is then formed on the surface of the first epitaxial layer and over the selected impurity. Finally, the selected impurity is driven through the first epitaxial layer and the second epitaxial layer to form the desired doped regions.

Abstract: A process for forming an isolated thin-film trench capacitor includes forming a first trench in a substrate and filling it with an electrically insulating material. A trench capacitor is formed in the first trench by forming first and second pluralities of conductive plates, such as polycrystalline silicon, separated by a layer of dielectric material. The first plurality of conductive plates are electrically connected together and the second plurality of conductive plates are electrically connected together. The dielectric material isolates the trench capacitor from the remainder of the chip. In one form, the trench capacitor comprises a plurality of second trenches in the electrically insulating material and the plurality of conductive plates are formed in the second trenches. In another form, a second trench is formed in the electrically insulating material and the trench capacitor is formed by interleaving conductive layers separated by dielectric material in the second trench.

Abstract: A lightly doped drain in an IGFET is provided by fabricating the transistor in a epitaxial layer lightly doped in the conductivity type of the channel for the device. The laterally reduced dopant concentration of the drain, and a lightly doped source if desired, is provided by leaving portions of the epitaxial layer unmodified.