Patents by Inventor Daniel J. Hubbard
Daniel J. Hubbard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126690Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
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Publication number: 20240086115Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Daniel J. Hubbard, Roy Leonard
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Publication number: 20240071510Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Giovanni Maria Paolucci, Dave Scott Ebsen, James Fitzpatrick, Akira Goda, Jeffrey S. McNeil, Umberto Siciliani, Daniel J. Hubbard, Walter Di Francesco, Michele Incarnati
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Publication number: 20240061592Abstract: A method includes receiving a request to perform a memory access operation, wherein the memory access operation includes a set of sub-operations, selecting a current quantization data structure from a plurality of current quantization data structures, wherein each current quantization data structure of the plurality of current quantization data structures maintains, for each sub-operation of the set of sub-operations, a respective current quantization value reflecting an amount of current that is consumed by the respective sub-operation based on a set of peak power management (PPM) operation parameters, and causing the memory access operation to be performed using PPM based on the current quantization data structure.Type: ApplicationFiled: August 8, 2023Publication date: February 22, 2024Inventors: Chulbum Kim, Jonathan S. Parry, Luca Nubile, Ali Mohammadzadeh, Biagio Iorio, Liang Yu, Jeremy Binfet, Walter Di Francesco, Daniel J. Hubbard, Luigi Pilolli
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Patent number: 11875061Abstract: A system includes a memory sub-system including a single-level cell (SLC) cache, a first multiple level cell (XLC) storage including a first XLC block, and a second XLC storage including a second XLC block. Data is indirectly written to the first XLC storage via the SLC cache in a first XLC write mode, and data is directly written to the second XLC storage in a second XLC write mode. The system further includes a processing device to perform operations including receiving data from a host system, in response to receiving the data, initiating a write operation to write the data to the first XLC storage and the second XLC storage, and causing subsets of the data to be alternatively written to the first XLC block in the first XLC write mode and to the second XLC block in the second XLC write mode using page level interleave.Type: GrantFiled: April 22, 2022Date of Patent: January 16, 2024Assignee: Micron Technology, Inc.Inventors: Daniel J. Hubbard, Roy Leonard
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Publication number: 20240004587Abstract: Systems and methods for specifying storage media types in write commands executable by storage devices are disclosed. An example system comprises: a plurality of memory devices and a controller operatively coupled to the memory devices, the controller configured to: receive a write command specifying a data item and an identifier of a data stream comprising the data item; determine, by parsing the identifier of the data stream, a data stream attribute shared by data items comprised by the data stream; identify, based on the data stream attribute, a memory device managed by the controller; and transmit, to the memory device, an instruction specifying the data item.Type: ApplicationFiled: September 14, 2023Publication date: January 4, 2024Inventor: Daniel J. Hubbard
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Patent number: 11861228Abstract: Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.Type: GrantFiled: October 29, 2021Date of Patent: January 2, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Karl D. Schuh, Ali Mohammadzadeh, Dheeraj Srinivasan, Daniel J. Hubbard, Luca Bert
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Patent number: 11853205Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.Type: GrantFiled: February 21, 2023Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
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Publication number: 20230350587Abstract: A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include receiving a request to perform an operation, determining whether to initiate a PPM priority override procedure, and in response to determining to initiate the PPM priority override procedure, performing the PPM priority override procedure to execute the operation. Performing the PPM priority override procedure includes reconfiguring each high current breakpoints as a respective low current breakpoint to execute the operation.Type: ApplicationFiled: April 20, 2023Publication date: November 2, 2023Inventors: Jeremy Binfet, Liang Yu, Jonathan S. Parry, Chulbum Kim, Daniel J. Hubbard, Suresh Rajgopal
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Patent number: 11803325Abstract: Systems and methods for specifying storage media types in write commands executable by storage devices are disclosed. An example system comprises: a plurality of memory devices and a controller operatively coupled to the memory devices, the controller configured to: receive a write command specifying a data item and an identifier of a data stream comprising the data item; determine, by parsing the identifier of the data stream, a data stream attribute shared by data items comprised by the data stream; identify, based on the data stream attribute, a memory device managed by the controller; and transmit, to the memory device, an instruction specifying the data item.Type: GrantFiled: March 27, 2018Date of Patent: October 31, 2023Assignee: Micron Technology, Inc.Inventor: Daniel J. Hubbard
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Publication number: 20230342081Abstract: A system includes a memory sub-system including a single-level cell (SLC) cache, a first multiple level cell (XLC) storage including a first XLC block, and a second XLC storage including a second XLC block. Data is indirectly written to the first XLC storage via the SLC cache in a first XLC write mode, and data is directly written to the second XLC storage in a second XLC write mode. The system further includes a processing device to perform operations including receiving data from a host system, in response to receiving the data, initiating a write operation to write the data to the first XLC storage and the second XLC storage, and causing subsets of the data to be alternatively written to the first XLC block in the first XLC write mode and to the second XLC block in the second XLC write mode using page level interleave.Type: ApplicationFiled: April 22, 2022Publication date: October 26, 2023Inventors: Daniel J. Hubbard, Roy Leonard
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Patent number: 11720493Abstract: System and methods are disclosed include a memory device and a processing device coupled to the memory device. The processing device can determine an amount of valid management units in a memory device of a memory sub-system. The processing device can then determine a surplus amount of valid management units on the memory device based on the amount of valid management units. The processing device can then configure a size of a cache of the memory device based on the surplus amount of valid management units.Type: GrantFiled: January 21, 2022Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Kevin R. Brandt, Peter Feeley, Kishore Kumar Muchherla, Yun Li, Sampath K. Ratnam, Ashutosh Malshe, Christopher S. Hale, Daniel J. Hubbard
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Publication number: 20230205455Abstract: Exemplary methods, apparatuses, and systems include receiving a request to perform an operation in memory. A subdivision of the memory to which the request is directed is determined. A command completion time based upon a command type for the operation and which subdivision of the memory to which the request is directed is determined. A command is sent to the memory for the operation. A request is sent to the memory for a status of the command based upon the determined command completion time.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Karl D. Schuh, Daniel J. Hubbard
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Publication number: 20230195615Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.Type: ApplicationFiled: February 21, 2023Publication date: June 22, 2023Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
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Patent number: 11593259Abstract: The present disclosure includes apparatuses and methods for directed sanitization of memory. One example method comprises, responsive to receiving a sanitization command, performing a deterministic garbage collection operation on a memory, wherein performing the deterministic garbage collection operation results in physical erasure of all invalid data stored on the memory without losing valid data stored on the memory.Type: GrantFiled: November 16, 2020Date of Patent: February 28, 2023Assignee: Micron Technology, Inc.Inventors: Jeffrey L. McVay, Daniel J. Hubbard, Robert W. Strong, Michael B. Danielson, Jonathan Tanguy
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Patent number: 11593261Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.Type: GrantFiled: July 13, 2021Date of Patent: February 28, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
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Publication number: 20230059543Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups.Type: ApplicationFiled: August 15, 2022Publication date: February 23, 2023Inventors: Andrea Giovanni Xotta, Dheeraj Srinivasan, Ali Mohammadzadeh, Karl D. Schuh, Guido Luciano Rizzo, Jung Sheng Hoei, Michele Piccardi, Tommaso Vali, Umberto Siciliani, Rohitkumar Makhija, June Lee, Aaron S. Yip, Daniel J. Hubbard
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Publication number: 20230043418Abstract: Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands. Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.Type: ApplicationFiled: October 29, 2021Publication date: February 9, 2023Inventors: Karl D. Schuh, Ali Mohammadzadeh, Dheeraj Srinivasan, Daniel J. Hubbard, Luca Bert
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Patent number: 11567689Abstract: A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to perform operations including detecting a failure to completely erase a block of the plurality of blocks in response to an attempted erasure of the block; receiving a blow fuse command in response to the failure to completely erase the block; and blowing a fuse, of the plurality of fuses, coupled with the block, to make the block electrically inaccessible to the control logic in response to receipt of the blow fuse command.Type: GrantFiled: August 5, 2021Date of Patent: January 31, 2023Assignee: Micron Technology, Inc.Inventors: Daniel J. Hubbard, Marc S. Hamilton, Kevin R. Brandt, William Akin
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Patent number: 11544188Abstract: Memory circuits including dynamically configurable cache cells are disclosed herein. The cache cells may be selectively and dynamically configured to select one or more bits per cell according to a real-time determination or characterization of a workload type.Type: GrantFiled: March 9, 2021Date of Patent: January 3, 2023Assignee: Micron Technology, Inc.Inventors: Yun Li, Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam