Patents by Inventor Daniel J. Jaeger
Daniel J. Jaeger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11056398Abstract: A method includes forming a gate cut opening by removing a sacrificial material from a portion of a dummy gate in a first dielectric over a substrate. The gate cut opening includes a lower portion in which the sacrificial material was located and an upper portion extending laterally over the first dielectric. Filling the gate cut opening with a second dielectric creates a gate cut isolation. Recessing the second dielectric creates a cap opening in the second dielectric; and filling the cap opening with a third dielectric creates a dielectric cap. The third dielectric is different than the second dielectric, e.g., oxide versus nitride, allowing forming of an interconnect in at least a portion of the third dielectric without the second, harder dielectric acting as an etch stop.Type: GrantFiled: July 22, 2019Date of Patent: July 6, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Daniel J. Jaeger, Naved A. Siddiqui, Shimpei Yamaguchi, Shreesh Narasimha
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Publication number: 20210028067Abstract: A method includes forming a gate cut opening by removing a sacrificial material from a portion of a dummy gate in a first dielectric over a substrate. The gate cut opening includes a lower portion in which the sacrificial material was located and an upper portion extending laterally over the first dielectric. Filling the gate cut opening with a second dielectric creates a gate cut isolation. Recessing the second dielectric creates a cap opening in the second dielectric; and filling the cap opening with a third dielectric creates a dielectric cap. The third dielectric is different than the second dielectric, e.g., oxide versus nitride, allowing forming of an interconnect in at least a portion of the third dielectric without the second, harder dielectric acting as an etch stop.Type: ApplicationFiled: July 22, 2019Publication date: January 28, 2021Inventors: Daniel J. Jaeger, Naved A. Siddiqui, Shimpei Yamaguchi, Shreesh Narasimha
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Method of forming semiconductor material in trenches having different widths, and related structures
Patent number: 10714376Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.Type: GrantFiled: June 25, 2018Date of Patent: July 14, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Chih-Chiang Chang, Haifeng Sheng, Jiehui Shu, Haigou Huang, Pei Liu, Jinping Liu, Haiting Wang, Daniel J. Jaeger -
METHOD OF FORMING SEMICONDUCTOR MATERIAL IN TRENCHES HAVING DIFFERENT WIDTHS, AND RELATED STRUCTURES
Publication number: 20190393077Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.Type: ApplicationFiled: June 25, 2018Publication date: December 26, 2019Inventors: Chih-Chiang Chang, Haifeng` Sheng, Jiehui Shu, Haigou Huang, Pei Liu, Jinping Liu, Haiting Wang, Daniel J. Jaeger -
Patent number: 9853116Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.Type: GrantFiled: December 14, 2015Date of Patent: December 26, 2017Assignee: International Business Machines CorporationInventors: Dechao Guo, Wilfried E. Haensch, Shu-jen Han, Daniel J. Jaeger, Yu Lu, Keith Kwong Hon Wong
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Publication number: 20160099332Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.Type: ApplicationFiled: December 14, 2015Publication date: April 7, 2016Inventors: Dechao Guo, Wilfried E. Haensch, Shu-jen Han, Daniel J. Jaeger, Yu Lu, Keith Kwong Hon Wong
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Patent number: 9299795Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.Type: GrantFiled: March 13, 2015Date of Patent: March 29, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Wilfried E. Haensch, Shu-jen Han, Daniel J Jaeger, Yu Lu, Keith Kwong Hon Wong
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Publication number: 20150187897Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.Type: ApplicationFiled: March 13, 2015Publication date: July 2, 2015Inventors: Dechao Guo, Wilfried E. Haensch, Shu-jen Han, Daniel J Jaeger, Yu Lu, Keith Kwong Hon Wong
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Patent number: 9041076Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.Type: GrantFiled: February 3, 2013Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Dechao Guo, Wilfried E. Haensch, Shu-jen Han, Daniel J Jaeger, Yu Lu, Keith Kwong Hon Wong
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Patent number: 9035430Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins.Type: GrantFiled: August 29, 2012Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Reinaldo A. Vega, Michael V. Aquilino, Daniel J. Jaeger
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Publication number: 20150044843Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins.Type: ApplicationFiled: September 18, 2014Publication date: February 12, 2015Inventors: Michael V. Aquilino, Daniel J. Jaeger, Reinaldo A. Vega
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Patent number: 8859388Abstract: A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device includes forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; and forming a sealing layer in the sealing recess over the STI fill.Type: GrantFiled: July 13, 2012Date of Patent: October 14, 2014Assignees: International Business Machines Corporation, GLOBALFOUNDRIES Inc.Inventors: Michael V. Aquilino, Xiang Hu, Daniel J. Jaeger, Byeong Y. Kim, Yong M. Lee, Ying Li, Reinaldo A. Vega
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Publication number: 20140217481Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.Type: ApplicationFiled: February 3, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Wilfried E. Haensch, Shu-jen Han, Daniel J. Jaeger, Yu Lu, Keith Kwong Hon Wong
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Patent number: 8704332Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.Type: GrantFiled: June 13, 2012Date of Patent: April 22, 2014Assignee: International Business Machines CorporationInventors: Christopher V. Baiocco, Daniel J. Jaeger, Carl J. Radens, Helen Wang
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Publication number: 20140061862Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins.Type: ApplicationFiled: August 29, 2012Publication date: March 6, 2014Applicant: International Business Machines CorporationInventors: Reinaldo A. VEGA, Michael V. AQUILINO, Daniel J. JAEGER
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Publication number: 20140015092Abstract: A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device includes forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; and forming a sealing layer in the sealing recess over the STI fill.Type: ApplicationFiled: July 13, 2012Publication date: January 16, 2014Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael V. Aquilino, Xiang Hu, Daniel J. Jaeger, Byeong Y. Kim, Yong M. Lee, Ying Li, Reinaldo A. Vega
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Patent number: 8629028Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.Type: GrantFiled: February 22, 2013Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Christopher V. Baiocco, Daniel J. Jaeger, Carl J. Radens, Helen Wang
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Publication number: 20130334618Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Applicant: International Business Machines CorporationInventors: Christopher V. Baiocco, Daniel J. Jaeger, Carl J. Radens, Helen Wang
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Publication number: 20130337624Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.Type: ApplicationFiled: February 22, 2013Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher V. Baiocco, Daniel J. Jaeger, Carl J. Radens, Helen Wang
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Patent number: 8569840Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.Type: GrantFiled: February 10, 2012Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Thomas A. Wallner, Ebenezer E. Eshun, Daniel J. Jaeger, Phung T. Nguyen