Abstract: A test system for a logic circuit in which virtual pins are coupled between logical networks and in which the virtual pins are free of any logic elements in common with the networks. A single latch control line, independent of the system clock of the networks, by applying three different control signals, controls switching between a test mode and a system mode and also controls latching and storing of data from a logic network. When the latch control line switches to the system mode it maintains the system mode independently of the cycling of the system clock. Further in the system mode, the virtual pins are transparent. In the test mode a string of virtual pins form a shift register which may be used to shift a test pattern by means of separate A,B clock signals into position for testing the logic networks.