Abstract: A first device port and a second device port are connected using a first cable and a second cable. The first device port and the second device port use a divisible number of lanes, X for communication. The first cable uses X? lanes, where X? is less than X. The second cable uses X-X? lanes, where X-X? is also less than X. If the first cable is disconnected or fails, then the second cable is used after a failover operation.

Abstract: A current generation, quad RAS, single CAS, stacked component (101) including four 4 Mb×4 bits 11/11 DRAMs (210-213) is arranged to emulate a next generation 16 Mb×4 bits 12/12 DRAM. The (24) bit address signal provided by memory controller (105) includes a row address of 12 bits and a column address of 12 bits. Each DRAM (210-213) within the current generation DRAM component (101) requires only 11 row address bits and 11 column address bits. The additional 1 row address bit and 1 column address bit are provided to decoder logic (103). The additional row address bit is decoded by the decoding logic (103) to direct the RAS signals over two of the four RAS lines (201-204), thereby activating the two signaled DRAMs. The additional column address bit is then decoded by decoding logic (103) to de-activate one of the two signaled DRAMs , leaving only one DRAM activated. CAS line (205) directs the CAS signal to all of the stacked DRAMs (210-213).

Abstract: A method and apparatus for addressing multi-bank memory. The method includes generating a first bank select and generating a first row address. The first row address is stored and presented as a second bank select during an activate portion of the memory cycle. During an access portion of the memory cycle, a first bank select is generated and the saved second bank select is retrieved from storage. The first bank select and retrieved second bank select identify a bank of memory. The apparatus includes a storage device for saving the second bank select. The second bank select may be stored based on the value of the first bank select.

Abstract: A method and apparatus for emulating a high storage capacity DRAM component. The emulation involves the use of a component containing multiple DRAMs, each having a lower storage capacity than that of the emulated DRAM, but having a cumulative storage capacity greater than or equal to that of the DRAM being emulated. Emulation entails the decoding of extra bits in an address signal from a controller for the high capacity DRAM to direct the output of DRAM control signals from a decoder to the multiple DRAM component so as to activate only one of the plurality of lower density DRAMs therein. Advantageously, the invention may be implemented so as to permit migration to a next generation DRAM device without altering wiring on the printed circuit board or changing the memory controller used to access the DRAM component.