Patents by Inventor Daniel J. Kouba

Daniel J. Kouba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4725986
    Abstract: An FET read only memory cell circuit is disclosed wherein word lines serve to augment the precharging of the bit lines. If an FET read only memory site is preprogrammed as a binary one, for example, then when its word line is pulsed, the bit line will be insured to have an affirmatively high potential, representing a binary one state. This improves the reliability of the operation of the circuit by minimizing the effects of charge leakage from the bit line.
    Type: Grant
    Filed: September 20, 1983
    Date of Patent: February 16, 1988
    Assignee: International Business Machines Corporation
    Inventor: Daniel J. Kouba
  • Patent number: 4525640
    Abstract: A "natural" threshold device is serially connected between the gate of an output depletion mode FET device and the input node to an FET device so as to provide current flow from the input node to the gate of the FET device as the input waveform begins to rise, and yet to provide sufficient resistance in the gate circuit of the depletion mode device so as to prevent backward flow of current from the gate as the potential of the output node rises. This increases the conductivity of the output load device, thereby providing a faster rise time for the output waveform.
    Type: Grant
    Filed: March 31, 1983
    Date of Patent: June 25, 1985
    Assignee: IBM Corporation
    Inventors: David H. Boyle, Daniel J. Kouba
  • Patent number: 4477738
    Abstract: A cross-coupled, latch-type clock driver circuit is disclosed which enables the carrying out of level sensitive scan design (LSSD) testing. During normal operation, the circuit functions to prevent a pair of input clock waveforms from overlapping. This is achieved by applying a low state to a control signal input which causes the circuit to perform a latching operation on the input clock waveforms by providing a conductive cross-coupled connection between a first and second NOR Logic elements connected to the input clock waveforms. Then the outputs of the NOR elements will be insured to be nonoverlapping. During the test mode, the input clock waveforms must not be latched, in order for LSSD testing to be carried out. This is achieved by applying a high state to the control signal input, which disables the cross-coupled connection between the NOR logic elements. The circuit then becomes transparent to the input clock waveforms, enabling testing operations to be performed.
    Type: Grant
    Filed: June 14, 1982
    Date of Patent: October 16, 1984
    Assignee: IBM Corporation
    Inventor: Daniel J. Kouba