Abstract: An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a circuit core (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.

Abstract: An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a circuit core (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.

Abstract: An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a core circuit (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.

Abstract: An electronic element (39?, 39, 40) having feedback control is provided by placing an inductive interposer (42) between the output connection or bus (382) and the input connection or bus (381), wherein the inductive interposer (42) forms part of a closed circuit (47) with the inductive interposer (42) substantially parallel with the output connection or bus (382) and input connection or bus (381) for a distance permitting significant inductive coupling therebetween. In a preferred embodiment, the closed circuit (47) containing the inductive interposer (42) comprises impedance ZT. By including various circuit elements (e.g., resistance, capacitance, and/or inductance) in ZT, the output-to-input feedback can be modified to advantage. This greatly increases the available design freedom, especially for power devices, such as for example, field effect, MOSFET, LDMOS. bipolar and other power devices that use substantially parallel input and output bus structures.

Abstract: An electronic element (39?, 39, 40) having feedback control is provided by placing an inductive interposer (42) between the output connection or bus (382) and the input connection or bus (381), wherein the inductive interposer (42) forms part of a closed circuit (47) with the inductive interposer (42) substantially parallel with the output connection or bus (382) and input connection or bus (381) for a distance permitting significant inductive coupling therebetween. In a preferred embodiment, the closed circuit (47) containing the inductive interposer (42) comprises impedance ZT. By including various circuit elements (e.g., resistance, capacitance, and/or inductance) in ZT, the output-to-input feedback can be modified to advantage. This greatly increases the available design freedom, especially for power devices, such as for example, field effect, MOSFET, LDMOS. bipolar and other power devices that use substantially parallel input and output bus structures.

Abstract: An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a core circuit (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.

Abstract: An ESD protection circuit (20) includes an ESD device (24) and an isolation diode element (30). The ESD device includes a drain-source junction isolated ESD transistor (26,28). The isolation diode element is coupled in series with the ESD device and configured for providing ESD protection to a transistor device (22) needing ESD protection. Responsive to ?Vgs conditions on a gate of the protected transistor device, the series coupled isolation diode element prevents a forward biasing of the drain-source junction of the ESD transistor prior to a breakdown condition of the isolation diode element. In addition, responsive to an ESD event sufficient to cause damage to the protected transistor device, the series coupled isolation diode element permits an occurrence of the breakdown condition. Furthermore, the ESD protection circuit can operate in both (i) a polarity of normal operation of the protected device and (ii) an opposite polarity other than in normal operation of the protected device.

Abstract: An integrated MIS capacitor structure has a bottom electrode, a capacitor dielectric overlying the bottom electrode, and a plurality of capacitor top plates overlying the capacitor dielectric. In one form each capacitor top plate has a principal dimension and a lesser dimension, wherein individual capacitor top plates of the plurality are arranged proximate and adjacent to one another in an array along respective principal dimensions thereof. The bottom electrode is shared among the plurality of capacitor top plates. At least one of a plurality of conductive stripes is positioned on opposite sides of each capacitor top plate along the principal dimension of a respective capacitor top plate. The structure also has a grounded top metal layer and an inter-level dielectric. An external ground via is disposed adjacent at least one side edge of the plurality of capacitor top plates.

Abstract: An integrated shunt capacitor comprises a bottom plate (86,88), a capacitor dielectric (92) overlying a portion of the bottom plate, a top plate (62) overlying the capacitor dielectric, a shield (74) overlying a portion of the top plate (62); and a metallization feature (70) disposed about and isolated from at least two sides of the top plate (62), the metallization feature (70) for coupling the bottom plate (86,88) to the shield (74). In one embodiment, an RF power transistor has an impedance matching network including an integrated shunt capacitor as described herein.

Abstract: An integrated MIS capacitor structure comprises a high quality factor shunt capacitor. The integrated MIS capacitor is configured with a large periphery and an external ground via to mitigate resistive losses in the bottom plate of the MIS shunt capacitor.

Abstract: A semiconductor device, such as a RF LDMOS, having a ground shield that has a pair of stacked metal layers. The first metal layer extends along the length of the semiconductor device and is formed on the upper surface of the semiconductor device body. The first layer has a series of regularly spaced apart lateral first slots. The second metal layer, coextensive with and located above the first metal layer, has a series of regularly spaced apart lateral second slots. The second slots overlie the spaces between the first slots, and the continuous portions of the second metal layer overlie the first slots. The slots are substantially parallel to wires extending over the ground shield. The ground shield is not limited to only two metal layers. The ground shield has a repeating unit design that facilitates automated design.

Abstract: An integrated shunt capacitor comprises a bottom plate (62), a capacitor dielectric (92) overlying a portion of the bottom plate, a top plate (64) overlying the capacitor dielectric, a shield (74) overlying a portion of the top plate; and a metallization feature (70) disposed about and isolated from at least two sides of the top plate, the metallization feature for coupling the bottom plate to the shield. In one embodiment, an RF power transistor has an impedance matching network including an integrated shunt capacitor as described herein.

Abstract: An ESD protection circuit (20) includes an ESD device (24) and an isolation diode element (30). The ESD device includes a drain-source junction isolated ESD transistor (26,28). The isolation diode element is coupled in series with the ESD device and configured for providing ESD protection to a transistor device (22) needing ESD protection. Responsive to ?Vgs conditions on a gate of the protected transistor device, the series coupled isolation diode element prevents a forward biasing of the drain-source junction of the ESD transistor prior to a breakdown condition of the isolation diode element. In addition, responsive to an ESD event sufficient to cause damage to the protected transistor device, the series coupled isolation diode element permits an occurrence of the breakdown condition. Furthermore, the ESD protection circuit can operate in both (i) a polarity of normal operation of the protected device and (ii) an opposite polarity other than in normal operation of the protected device.

Abstract: A semiconductor device (10) having a gate (15), a source (19), and a drain (20) with a gate bus (25) and first ground shield (24) patterned from a first metal layer and a second ground shield (31) patterned from a second metal layer. The first ground shield (24) and the second ground shield (31) lower the capacitance of device (10) making it suitable for high frequency applications and housing in a plastic package.

Abstract: A semiconductor device (10) having a gate (15), a source (19), and a drain (20) with a gate bus (25) and first ground shield (24) patterned from a first metal layer and a second ground shield (31) patterned from a second metal layer. The first ground shield (24) and the second ground shield (31) lower the capacitance of device (10) making it suitable for high frequency applications and housing in a plastic package.

Abstract: An electrostatic discharge (ESD) protection circuit (20) includes an active load circuit (22) connected to a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor (21) having a Lightly Doped Drain (LDD). The active load circuit includes a current limiting circuit (26) and a load transistor (27). The ESD protection circuit (20) operates to protect a power transistor (16) from damage due to an electrostatic charge. During an ESD event, the LDMOS transistor (21) enters avalanche breakdown after the voltage of the electrostatic charge exceeds the breakdown voltage of the LDMOS transistor (21). The ESD protection circuit (20) provides a low resistance path during an ESD event to dissipate the electrostatic charge.

Abstract: A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.