Patents by Inventor Daniel J. Lichtenwalner

Daniel J. Lichtenwalner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998418
    Abstract: Power semiconductor devices include multi-layer inter-metal dielectric patterns that include at least one reflowed dielectric material pattern and at least one non-reflowable dielectric material pattern. In other embodiments, power semiconductor devices include reflowed inter-metal dielectric patterns that are formed using sacrificial structures such as dams to limit the lateral spread of the reflowable dielectric material of the inter-metal dielectric pattern during the reflow process. The inter-metal dielectric patterns may have improved shapes and performance.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 4, 2021
    Assignee: CREE, INC.
    Inventors: Edward R. Van Brunt, Daniel J. Lichtenwalner, Shadi Sabri
  • Publication number: 20210098568
    Abstract: Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.
    Type: Application
    Filed: November 19, 2020
    Publication date: April 1, 2021
    Inventors: Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull
  • Patent number: 10861931
    Abstract: Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: December 8, 2020
    Assignee: Cree, Inc.
    Inventors: Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull
  • Publication number: 20200365708
    Abstract: Power semiconductor devices include multi-layer inter-metal dielectric patterns that include at least one reflowed dielectric material pattern and at least one non-reflowable dielectric material pattern. In other embodiments, power semiconductor devices include reflowed inter-metal dielectric patterns that are formed using sacrificial structures such as dams to limit the lateral spread of the reflowable dielectric material of the inter-metal dielectric pattern during the reflow process. The inter-metal dielectric patterns may have improved shapes and performance.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Inventors: Edward R. Van Brunt, Daniel J. Lichtenwalner, Shadi Sabri
  • Publication number: 20180166530
    Abstract: Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.
    Type: Application
    Filed: December 8, 2016
    Publication date: June 14, 2018
    Inventors: Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull
  • Patent number: 9972677
    Abstract: Methods of forming a power semiconductor device are provided in which a semiconductor drift layer that is doped with impurities having a first conductivity type is formed on a semiconductor substrate. A portion of the semiconductor drift layer is removed to form a recessed region in the semiconductor drift layer and to define a first semiconductor pillar. Impurities having a second conductivity type that is opposite the first conductivity type are implanted into a first sidewall of the semiconductor drift layer that is exposed by the recessed region to convert a portion of the first semiconductor pillar into a second semiconductor pillar. A third semiconductor pillar is formed in the recessed region.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 15, 2018
    Assignee: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Vipindas Pala, Lin Cheng, Daniel J. Lichtenwalner
  • Patent number: 9887287
    Abstract: Semiconductor devices include a semiconductor layer structure having a wide band-gap semiconductor drift region having a first conductivity type. A gate trench is provided in an upper portion of the semiconductor layer structure, the gate trench having first and second opposed sidewalls that extend in a first direction in the upper portion of the semiconductor layer structure. These devices further include a deep shielding pattern having a second conductivity type that is opposite the first conductivity type in the semiconductor layer structure underneath a bottom surface of the gate trench, and a deep shielding connection pattern that has the second conductivity type in the first sidewall of the gate trench. The devices include a semiconductor channel region that has the first conductivity type in the second sidewall of the gate trench.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 6, 2018
    Assignee: Cree, Inc.
    Inventors: Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull, Alexander V. Suvorov, Craig Capell
  • Publication number: 20170345891
    Abstract: Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/?1.5° of a crystallographic axis of the silicon carbide material forming the drift region.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Inventors: Edward Robert Van Brunt, Alexander V. Suvorov, Vipindas Pala, Daniel J. Lichtenwalner, Qingchun Zhang
  • Publication number: 20170047396
    Abstract: A semiconductor device has a drift region having an upper surface and a lower surface. A first contact is on the upper surface of the drift region and a second contact is on the lower surface of the drift region. The drift region includes a first semiconductor pillar that has a tapered sidewall and that is doped with first conductivity type impurities and a second semiconductor pillar on the tapered sidewall of the first semiconductor pillar, the second semiconductor pillar doped with second conductivity type impurities that have an opposite conductivity from the first conductivity type impurities.
    Type: Application
    Filed: October 31, 2016
    Publication date: February 16, 2017
    Inventors: Edward Robert Van Brunt, Vipindas Pala, Lin Cheng, Daniel J. Lichtenwalner
  • Patent number: 9515199
    Abstract: A semiconductor device has a drift region having an upper surface and a lower surface. A first contact is on the upper surface of the drift region and a second contact is on the lower surface of the drift region. The drift region includes a first semiconductor pillar that has a tapered sidewall and that is doped with first conductivity type impurities and a second semiconductor pillar on the tapered sidewall of the first semiconductor pillar, the second semiconductor pillar doped with second conductivity type impurities that have an opposite conductivity from the first conductivity type impurities.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: December 6, 2016
    Assignee: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Vipindas Pala, Lin Cheng, Daniel J. Lichtenwalner
  • Publication number: 20160197201
    Abstract: A semiconductor device has a drift region having an upper surface and a lower surface. A first contact is on the upper surface of the drift region and a second contact is on the lower surface of the drift region. The drift region includes a first semiconductor pillar that has a tapered sidewall and that is doped with first conductivity type impurities and a second semiconductor pillar on the tapered sidewall of the first semiconductor pillar, the second semiconductor pillar doped with second conductivity type impurities that have an opposite conductivity from the first conductivity type impurities.
    Type: Application
    Filed: January 2, 2015
    Publication date: July 7, 2016
    Inventors: Edward Robert Van Brunt, Vipindas Pala, Lin Cheng, Daniel J. Lichtenwalner
  • Publication number: 20110147764
    Abstract: A metal-insulator-semiconductor field-effect transistor (MISFET) includes a semiconductor layer with source and drain regions of a first conductivity type spaced apart therein. A channel region of a first conductivity type extends between the source and drain regions. A gate contact is on the channel region. A dielectric channel depletion layer is between the gate contact and the channel region. The dielectric channel depletion layer provides a net charge having the same polarity as the first conductivity type charge carriers, and which may deplete the first conductivity type charge carriers from an adjacent portion of the channel region when no voltage is applied to the gate contact.
    Type: Application
    Filed: November 4, 2009
    Publication date: June 23, 2011
    Inventors: Sarit Dhar, Sei-Hyung Ryu, Veena Misra, Daniel J. Lichtenwalner