Abstract: The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.

Abstract: A method for etching a differential metal gate structure on a substrate is described. The differential metal gate structure includes a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein the metal gate layer comprises a different thickness at different regions on the substrate. The metal gate layer is patterned by using a plasma etching process, wherein at least one etch step includes forming plasma using a halogen-containing gas and at least one etch step includes forming plasma using an additive gas having as atomic constituents C, H, and F.

Abstract: The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.

Abstract: A method for etching a differential metal gate structure on a substrate is described. The differential metal gate structure includes a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein the metal gate layer comprises a different thickness at different regions on the substrate. The metal gate layer is patterned by using a plasma etching process, wherein at least one etch step includes forming plasma using a halogen-containing gas and at least one etch step includes forming plasma using an additive gas having as atomic constituents C, H, and F.

Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.

Abstract: The invention can provide apparatus and methods of creating metal gate structures on wafers in real-time using Lithography-Etch-Lithography-Etch (LELE) processing sequence. Real-time data and/or historical data associated with LELE processing sequences can be fed forward and/or fed back as fixed variables or constrained variables in internal-Integrated-Metrology modules (i-IMM) to improve the accuracy of the metal gate structures.

Abstract: The invention can provide a method of processing a substrate using Spacer-Optimization (S-O) processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures. In addition, the S-O processing sequences can include one or more deposition procedures, one or more partial-etch procedures, one or more chemical oxide removal (COR)-etch procedures, one or more optimization procedures, one or more evaluation procedures, and/or one or more verification procedures.

Abstract: A method of creating a virtual profile library includes obtaining a reference signal. The reference signal is compared to a plurality of signals in a first library. The reference signal is compared to a plurality of signals in a second library. A virtual profile data space is created when first and second matching criteria are not met. The virtual profile data space is created using differences between a profile data spaces associated with the first and second libraries. A first virtual profile signal is created in the virtual profile data space. A difference is calculated between the reference signal and the first virtual profile signal. The difference is compared to a virtual profile library creation criteria. If the virtual profile library creation criteria is met, the first virtual profile signal and the virtual profile data, associated with the first virtual profile signal is stored.

Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.

Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.

Abstract: A method of refining a virtual profile library includes obtaining a reference signal measured off a reference structure on a semiconductor wafer with a metrology device. A best match is selected of the reference signal in a virtual profile data space. The virtual profile data space has data points with specified accuracy values. The data points represent virtual profile parameters and associated virtual profile signals. The virtual profile parameters characterize the profile of an integrated circuit structure. The best match being a data point of the profile data space with a signal closest to the reference signal. Refined virtual profile parameters are determined corresponding to the reference signal based on the virtual profile parameters of the selected virtual profile signal using a refinement procedure.