Abstract: Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an SoC may include a memory to store a plurality of embedded values correspondingly associated with a plurality of architecturally identical cores. Each embedded value may indicate a default voltage for a respective one of the plurality of architecturally identical cores. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to provide access from outside the multicore processor SoC to individually configure voltages of the plurality of architecturally identical cores to values that are different than the values of the default voltages. Other embodiments may be described and/or claimed.

Abstract: According to one embodiment of the invention, a processor includes a power control unit, an interface to software during runtime that permits the software to set a plurality of power management constraint parameters for the power control unit during runtime of the processor without a reboot of the processor, and a storage element to store a respective lock bit for each of the plurality of power management constraint parameters to disable the interface from changing a respective constraint parameter when set.

Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.

Abstract: Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an SoC may include a memory to store a plurality of embedded values correspondingly associated with a plurality of architecturally identical cores. Each embedded value may indicate a default voltage for a respective one of the plurality of architecturally identical cores. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to provide access from outside the multicore processor SoC to individually configure voltages of the plurality of architecturally identical cores to values that are different than the values of the default voltages. Other embodiments may be described and/or claimed.

Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.

Abstract: An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.

Abstract: Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an SoC may include a memory to store a plurality of embedded values correspondingly associated with a plurality of architecturally identical cores. Each embedded value may indicate a default voltage for a respective one of the plurality of architecturally identical cores. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to provide access from outside the multicore processor SoC to individually configure voltages of the plurality of architecturally identical cores to values that are different than the values of the default voltages. Other embodiments may be described and/or claimed.

Abstract: Systems and methods consistent with the present disclosure include techniques for dynamic system performance tuning (DSPT). Techniques for DSPT include identifying an active software application during a user session and applying an application-specific profile that defines different system-hardware operating states of a computing system to enhance the performance of the active software application.

Abstract: According to one embodiment of the invention, a processor includes a power control unit, an interface to software during runtime that permits the software to set a plurality of power management constraint parameters for the power control unit during runtime of the processor without a reboot of the processor, and a storage element to store a respective lock bit for each of the plurality of power management constraint parameters to disable the interface from changing a respective constraint parameter when set.

Abstract: Systems and methods consistent with the present disclosure include techniques for dynamic system performance tuning (DSPT). Techniques for DSPT include identifying an active software application during a user session and applying an application-specific profile that defines different system-hardware operating states of a computing system to enhance the performance of the active software application.

Abstract: Methods and apparatus related to on-the-fly performance adjustment techniques for solid state storage devices are described. In one embodiment, a controller logic controls access to one or more non-volatile memory devices. The controller logic causes a change in an operational frequency of one or more of: the controller logic, a bus that couples the one or more non-volatile memory devices to the controller logic, and one or more of the one or more non-volatile memory devices. Also, the controller logic is capable of causing the change in the operational frequency in response to a command. Furthermore, changing power limits is made possible to scale solid state storage device performance based on system capabilities. Other embodiments are also disclosed and claimed.

Abstract: In an embodiment, a processor includes a power control unit (PCU) to control power delivery to components of the processor and further including a storage having an overclock lock indicator which when set is to prevent a user from updating configuration settings associated with overclocking performance of the processor within an operating system (OS) environment. Other embodiments are described and claimed.

Abstract: A method and apparatus include providing a printed circuit board (PCB) having at least one light permeable layer, at least one non-light permeable layer having at least one void therethrough that may be vertically aligned with the at least one light permeable layer, and a source of illumination to simultaneously illuminate through the void and the at least one light permeable layer.

Abstract: A circuit is presented including switches connected to registers. The registers control the switches. The switches are connected to universal serial bus (USB) ports based on a USB device bandwidth balancing process. Also presented is a method determining allocation of USB root hubs. The method also switching USB root hub USB device assignments.

Abstract: A circuit is presented including switches connected to registers. The registers control the switches. The switches are connected to universal serial bus (USB) ports based on a USB device bandwidth balancing process. Also presented is a method determining allocation of USB root hubs. The method also switching USB root hub USB device assignments.