Abstract: A method of and system for frequency clocking in a processor core are disclosed. In this system, at least one processor core is provided, and that at least one processor core has a clocking subsystem for generating an analog output clock signal at a variable frequency. Digital frequency control data and an analog signal are both transmitted to that at least one processor core; and that processor core uses the received analog signal and digital frequency control data to set the frequency of the output clock signal of the clocking subsystem. In a preferred implementation, multiple cores are asynchronously clocked and the core frequencies are independently set.

Abstract: A server Input/Output (I/O) drawer for holding one or more communication cards and one or more I/O cards includes an outer housing, a back plane within the outer housing that divides the drawer into a front portion and back portion, the back plane including a front side and a backside and configured to receive the one or more I/O cards and the one or more communications cards, and an air movement device (AMD) disposed within the front portion, a distribute current assembly (DCA) that receives a voltage from an external source and supplies power, through the backplane, to the AMD.

Abstract: Optical devices, components and methods for mounting optical fibers and for side-coupling light to/from optical fibers using a modified silicon V-groove, or silicon V-groove array, wherein V-grooves, which are designed for precisely aligning/spacing optical fibers, are “recessed” below the surface of the silicon. Optical fibers can be recessed below the surface of the silicon substrate such that a precisely controlled portion of the cladding layer extending above the silicon surface can be removed (lapped). With the cladding layer removed, the separation between the fiber core(s) and optoelectronic device(s) can be reduced resulting in improved optical coupling when the optical fiber silicon array is connected to, e.g., a VCSEL array.

Abstract: A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including multiple cores. The system reference oscillator clock frequency provides a reference frequency to a local oscillator. The local oscillator supplies a core clock frequency to at least one of the cores. The method further includes adjusting the local oscillator to output the core clock frequency at a frequency greater than the system reference oscillator clock frequency as a function of digital frequency characteristic data associated with the core or cores. The method supports extendibility to larger systems and may support enhanced power management through frequency adjustments at the core level.

Abstract: A method of optimizing performance of a multi-core chip having a plurality of cores includes the steps of determining a Vdd-frequency SCHMOO characteristic for each of the plurality of cores individually; saving data indicative of the Vdd-frequency SCHMOO characteristics for each of the plurality of cores; configuring the cores to obtain a configuration providing at least one of optimum power consumption and optimum performance, for a given workload, based on the saved data; and saving the configuration such that it may be updated and used on at least one of a periodic and a continual basis.

Abstract: Disclosed are a method of and system for digital frequency clocking in a processor core. At least one-processor core is provided, and that processor core has a clocking subsystem for generating an output clock signal, which may be an analog signal at a variable frequency. Digital frequency control data are transmitted or distributed to the processor core; and that one processor core receives the digital frequency control data transmitted to the core, and uses that received digital frequency control data to set the frequency of the output clock signal of the clocking subsystem of the processor core. Preferably, multiple cores are asynchronously clocked and the core frequencies are independently set, and, there is no phase relationship between the core clocks.

Abstract: A (DFLL) circuit residing on a local core of a multi-core microprocessor for generating a local core clock with a frequency for driving the local core includes a micro-controller configured to receive core characterizing digital data; a ring oscillator configured to generate the local core clock for the local core, and having a delay chain disposed between an output and a feedback input of the ring oscillator, the delay chain having delay taps each receiving the local core clock enabling quantum changes in the frequency of the local core clock; and a counter device configured to continually validate the frequency by generating a digital signal representative of the frequency to the micro-controller, the micro-controller compares the frequency of the local core clock to a desired clock frequency, and selects one of the delay taps based on the comparison to adjust the frequency value of the local core clock.

Abstract: A (DFLL) circuit residing on a local core of a multi-core microprocessor for generating a local core clock with a frequency for driving the local core includes a micro-controller configured to receive core characterizing digital data; a ring oscillator configured to generate the local core clock for the local core, and having a delay chain disposed between an output and a feedback input of the ring oscillator, the delay chain having delay taps each receiving the local core clock enabling quantum changes in the frequency of the local core clock; and a counter device configured to continually validate the frequency by generating a digital signal representative of the frequency to the micro-controller, the micro-controller compares the frequency of the local core clock to a desired clock frequency, and selects one of the delay taps based on the comparison to adjust the frequency value of the local core clock.

Abstract: A system, method and storage medium for providing redundant I/O access between a plurality of interconnected processor nodes and I/O resources. The method includes determining whether a primary path between the interconnected processor nodes and the I/O resources is operational, where the primary path includes a first processor node and a primary multiplexer. If the primary path is operational, the transactions are routed via the primary path. If the primary path is not operational, the transactions are routed between the interconnected processor nodes and the I/O resources via an alternate path that includes a second processor node and an alternate multiplexer.

Abstract: A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including multiple cores. The system reference oscillator clock frequency provides a reference frequency to a local oscillator. The local oscillator supplies a core clock frequency to at least one of the cores. The method further includes adjusting the local oscillator to output the core clock frequency at a frequency greater than the system reference oscillator clock frequency as a function of digital frequency characteristic data associated with the core or cores. The method supports extendibility to larger systems and may support enhanced power management through frequency adjustments at the core level.

Abstract: A method and systems for a digital frequency locked loop in a multi-core processor are provided. The method includes applying a dither modulation signal at a dither modulation frequency to modulate an output frequency to provide a clock signal to a core of the multi-core processor. The method further includes filtering a feedback signal of the output frequency with respect to a target frequency. The method additionally includes determining a frequency error in the filtered feedback signal as a function of alignment of the output frequency to the target frequency, and adjusting the output frequency in response to the frequency error.

Abstract: Optical devices, components and methods for mounting optical fibers and for side-coupling light to/from optical fibers using a modified silicon V-groove, or silicon V-groove array, wherein V-grooves, which are designed for precisely aligning/spacing optical fibers, are “recessed” below the surface of the silicon. Optical fibers can be recessed below the surface of the silicon substrate such that a precisely controlled portion of the cladding layer extending above the silicon surface can be removed (lapped). With the cladding layer removed, the separation between the fiber core(s) and optoelectronic device(s) can be reduced resulting in improved optical coupling when the optical fiber silicon array is connected to, e.g., a VCSEL array.

Abstract: A method of optimizing performance of a multi-core chip having a plurality of cores includes the steps of determining a Vdd-frequency SCHMOO characteristic for each of the plurality of cores individually; saving data indicative of the Vdd-frequency SCHMOO characteristics for each of the plurality of cores; configuring the cores to obtain a configuration providing at least one of optimum power consumption and optimum performance, for a given workload, based on the saved data; and saving the configuration such that it may be updated and used on at least one of a periodic and a continual basis.

Abstract: Optical devices, components and methods for mounting optical fibers and for side-coupling light to/from optical fibers using a modified silicon V-groove, or silicon V-groove array, wherein V-grooves, which are designed for precisely aligning/spacing optical fibers, are “recessed” below the surface of the silicon. Optical fibers can be recessed below the surface of the silicon substrate such that a precisely controlled portion of the cladding layer extending above the silicon surface can be removed (lapped). With the cladding layer removed, the separation between the fiber core(s) and optoelectronic device(s) can be reduced resulting in improved optical coupling when the optical fiber silicon array is connected to, e.g., a VCSEL array.

Abstract: Disclosed are a method of and system for digital frequency clocking in a processor core. At least one-processor core is provided, and that processor core has a clocking subsystem for generating an output clock signal, which may be an analog signal at a variable frequency. Digital frequency control data are transmitted or distributed to the processor core; and that one processor core receives the digital frequency control data transmitted to the core, and uses that received digital frequency control data to set the frequency of the output clock signal of the clocking subsystem of the processor core. Preferably, multiple cores are asynchronously clocked and the core frequencies are independently set, and, there is no phase relationship between the core clocks.

Abstract: A method of and system for frequency clocking in a processor core are disclosed. In this system, at least one processor core is provided, and that at least one processor core has a clocking subsystem for generating an analog output clock signal at a variable frequency. Digital frequency control data and an analog signal are both transmitted to that at least one processor core; and that processor core uses the received analog signal and digital frequency control data to set the frequency of the output clock signal of the clocking subsystem. In a preferred implementation, multiple cores are asynchronously clocked and the core frequencies are independently set.

Abstract: An optoelectronic assembly for a computer system includes an electronic chip(s), a substrate, an electrical signaling medium, an optoelectronic transducer, and an optical coupling guide. The electronic chip(s) is in communication with the substrate, which is in communication with a first end of the electrical signaling medium. A second end of the electrical signaling medium is in communication with the optoelectronic transducer, and includes the optical coupling guide for aligning an optical signaling medium with the optoelectronic transducer. An electrical signal from the electronic chip is communicated to the optoelectronic transducer via the substrate and the electrical signaling medium. The optical transducer and electronic chip(s) share a common heat spreader, and communication to other groups of electronic chip(s) is done without the need for communication via a second level electrical package.

Abstract: Optical devices, components and methods for mounting optical fibers and for side-coupling light to/from optical fibers using a modified silicon V-groove, or silicon V-groove array, wherein V-grooves, which are designed for precisely aligning/spacing optical fibers, are “recessed” below the surface of the silicon. Optical fibers can be recessed below the surface of the silicon substrate such that a precisely controlled portion of the cladding layer extending above the silicon surface can be removed (lapped). With the cladding layer removed, the separation between the fiber core(s) and optoelectronic device(s) can be reduced resulting in improved optical coupling when the optical fiber silicon array is connected to, e.g., a VCSEL array.

Abstract: An integrated optical transducer assembly includes a substrate and an optoelectronic array attached to the substrate. The optoelectronic array further includes a plurality of individual subunits bonded together to form a single array, with each of the subunits including a defined number of individual optoelectronic elements associated therewith. The elastomeric material maintains an original alignment between the plurality of subunits.

Abstract: An optoelectronic assembly for an electronic system includes a support electronic chip set configured for at least one of providing multiplexing, demultiplexing, coding, decoding and optoelectronic transducer driving and receive functions. A first substrate having a first surface and an opposite second surface is in communication with the support electronic chip set via the first surface while a second substrate is in communication with the second surface of the first substrate. The second substrate is configured for mounting at least one of data processing, data switching and data storage chips. An optoelectronic transducer is in signal communication with the support electronic chip set and an optical fiber array is aligned at a first end with the optoelectronic transducer and with an optical signaling medium at a second end.