Abstract: A computer system has a universal channel and control unit to interface, with a minimum complexity, to a plurality of different I/O adapters such as a Token Ring adapter or an Ethernet adapter. The system comprises a main processor with main memory, an I/O processor coupled to the main processor by a bus, and a channel program which runs on the I/O processor. The channel program accesses the processor and main memory. The channel program and main processor communicate with a first I/O program protocol. A control unit program also runs on the I/O processor and interfaces the channel program to a plurality of different I/O adapters with a second relatively simple, universal I/O program protocol. Each of the I/O adapters also has a different I/O program protocol than the other I/O adapters and the first I/O protocol, for communication with their respective device.

Abstract: The performance of a multi-microprocessor implemented data processing system that emulates a mainframe system is enhanced and optimized in view of space and power constraints for purposes of address translation by providing RAM-based storage means of predetermined depth and width to function as a page address table. The storage means depth is set to at least provide bit space to represent the total number of fixed size pages possible in a given virtual memory space. The width of the storage means is set to at least provide bit space to represent the largest page number that might be encountered in the available real memory and to accommodate a predetermined number of bits that flag information pertinent to translation and system performance. Circuit means, including microcode, is provided for initializing and updating the contents of the storage means as required.

Abstract: Synchronization of peripheral operation with that of a processor in a multi-microprocessor implemented data processing system is achieved by bus cycle alteration. A logic circuit is provided for monitoring the condition of a peripheral's status bits and for preventing an appropriate processor control signal from completing the present bus cycle if the peripheral of interest is not able to accept an access. The peripheral of interest is readily identified by providing unique memory mapped locations, one for each system peripheral, that are responsively connected to the logic circuit.