Patents by Inventor Daniel Jaeger
Daniel Jaeger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11958871Abstract: The present invention relates to novel compounds which are particularly useful as inhibitors of bacterial glutaminyl cyclases (bacQC); pharmaceutical compositions comprising such compounds; compounds and/or pharmaceutical compositions for use in methods for treatment, in particular for use in the treatment of periodontitis and related conditions; as well as to crystals comprising bacterial glutaminyl cyclases, methods for identifying candidate compounds which may associate with the binding pocket of a bacQC and/or are bacQC inhibitors.Type: GrantFiled: February 22, 2019Date of Patent: April 16, 2024Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Christian Jäger, Linda Liebe, Daniel Ramsbeck, Miriam Linnert, Stefanie Geissler, Anke Piechotta, Diane Meitzner, Holger Cynis, Mirko Buchholz
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Patent number: 11907685Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.Type: GrantFiled: November 8, 2019Date of Patent: February 20, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Judson R. Holt, Julien Frougier, Ryan W. Sporer, George R. Mulfinger, Daniel Jaeger
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Publication number: 20210141610Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.Type: ApplicationFiled: November 8, 2019Publication date: May 13, 2021Applicant: GLOBALFOUNDRIES U.S. Inc.Inventors: Judson R. Holt, Julien Frougier, Ryan W. Sporer, George R. Mulfinger, Daniel Jaeger
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Patent number: 10991796Abstract: A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.Type: GrantFiled: December 24, 2018Date of Patent: April 27, 2021Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Lin Hu, Veeraraghavan S. Basker, Brian J. Greene, Kai Zhao, Daniel Jaeger, Keith Tabakman, Christopher Nassar
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Patent number: 10971625Abstract: A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.Type: GrantFiled: June 30, 2019Date of Patent: April 6, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Michael V Aquilino, Daniel Jaeger, Man Gu, Bradley Morgenfeld, Haiting Wang, Kavya Sree Duggimpudi, Wang Zheng
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Patent number: 10947681Abstract: A protective construction, such as a fence for a race track, may include a device for energy dissipation, e.g., in line with a guy wire. In some examples, the energy dissipation device may have a braking profile and a cutting unit having at least one blade that can be pulled through the braking profile along its longitudinal axis.Type: GrantFiled: October 10, 2017Date of Patent: March 16, 2021Assignee: Trumer Schutzbauten Ges.m.b.HInventors: Gernot Stelzer, Daniel Jäger
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Patent number: 10930549Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.Type: GrantFiled: September 17, 2019Date of Patent: February 23, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Jinsheng Gao, Daniel Jaeger, Chih-Chiang Chang, Michael Aquilino, Patrick Carpenter, Junsic Hong, Mitchell Rutkowski, Haigou Huang, Huy Cao
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Patent number: 10907693Abstract: The invention relates to a clutch unit for a motor vehicle, comprising: a clutch, the clutch having an axially stationary, rotatable coupling element with an axially extending toothing, and an axially displaceable, rotatable mating element with an axially extending mating toothing, the mating element being displaceable into a first position and a second position; and a sensor unit, the sensor unit being disposed radially in relation to the axial extension of the toothing of the coupling element such that the sensor unit senses the toothing of the coupling element. When the mating element is in the first position and when it is in the second position, the sensor unit detects a sensor signal via which the rotational speed of the coupling element and the first position of the mating element, the second position of the mating element, or a position of the mating element between the first position and the second position can be determined.Type: GrantFiled: June 22, 2017Date of Patent: February 2, 2021Assignee: MAGNA POWERTRAIN GMBH & CO KGInventors: Thomas Eisl, Daniel Jäger, Mario Tigelhardt, Johannes Unterkofler
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Publication number: 20200411689Abstract: A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.Type: ApplicationFiled: June 30, 2019Publication date: December 31, 2020Inventors: MICHAEL V. AQUILINO, DANIEL JAEGER, MAN GU, BRADLEY MORGENFELD, HAITING WANG, KAVYA SREE DUGGIMPUDI, WANG ZHENG
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Patent number: 10833160Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.Type: GrantFiled: April 17, 2019Date of Patent: November 10, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Michael Aquilino, Daniel Jaeger, Naved Siddiqui, Jessica Dechene, Daniel J. Dechene, Shreesh Narasimha, Natalia Borjemscaia
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Publication number: 20200335591Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.Type: ApplicationFiled: April 17, 2019Publication date: October 22, 2020Inventors: Michael Aquilino, Daniel Jaeger, Naved Siddiqui, Jessica Dechene, Daniel J. Dechene, Shreesh Narasimha, Natalia Borjemscaia
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Patent number: 10755982Abstract: One illustrative method disclosed herein includes forming 1st and 2nd sacrificial gate structures for, respectively, 1st and 2nd devices, removing 1st and 2nd sacrificial gate electrodes from the 1st and 2nd sacrificial gate structures so as to at least partially define, respectively, 1st and 2nd replacement gate (RMG) cavities, and removing the 2nd sacrificial gate insulation layer from the 2nd RMG cavity while leaving the 1st sacrificial gate insulation layer in position in the 1st RMG cavity. The method also includes forming a conformal gate insulation layer in both the 1st and 2nd RMG cavities, removing the conformal gate insulation layer and the 1st sacrificial gate insulation layer from the 1st RMG cavity while leaving the conformal gate insulation layer in the 2nd RMG cavity, and performing an oxidation process to form an interfacial gate insulation layer only in the 1st RMG cavity.Type: GrantFiled: July 11, 2019Date of Patent: August 25, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Abu Naser M. Zainuddin, Wei Ma, Daniel Jaeger, Joseph Versaggi, Jae Gon Lee, Thomas Kauerauf
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Publication number: 20200203480Abstract: A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.Type: ApplicationFiled: December 24, 2018Publication date: June 25, 2020Applicant: GLOBALFOUNDRIES INC.Inventors: Lin HU, Veeraraghavan S. BASKER, Brian J. GREENE, Kai ZHAO, Daniel JAEGER, Keith TABAKMAN, Christopher NASSAR
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Patent number: 10644156Abstract: Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.Type: GrantFiled: March 12, 2018Date of Patent: May 5, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Michael Aquilino, Patrick Carpenter, Xusheng Wu, Haigou Huang
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Publication number: 20200056337Abstract: A protective construction, such as a fence for a race track, may include a device for energy dissipation, e.g., in line with a guy wire. In some examples, the energy dissipation device may have a braking profile and a cutting unit having at least one blade that can be pulled through the braking profile along its longitudinal axis.Type: ApplicationFiled: October 10, 2017Publication date: February 20, 2020Inventors: Gernot STELZER, Daniel JÄGER
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Publication number: 20200013672Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.Type: ApplicationFiled: September 17, 2019Publication date: January 9, 2020Inventors: Jinsheng GAO, Daniel JAEGER, Chih-Chiang CHANG, Michael AQUILINO, Patrick CARPENTER, Junsic HONG, Mitchell RUTKOWSKI, Haigou HUANG, Huy CAO
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Patent number: 10522639Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: GrantFiled: June 29, 2019Date of Patent: December 31, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Patent number: 10460986Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.Type: GrantFiled: January 29, 2018Date of Patent: October 29, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jinsheng Gao, Daniel Jaeger, Chih-Chiang Chang, Michael Aquilino, Patrick Carpenter, Junsic Hong, Mitchell Rutkowski, Haigou Huang, Huy Cao
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Publication number: 20190326408Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.Type: ApplicationFiled: June 29, 2019Publication date: October 24, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Daniel Jaeger, Haigou Huang, Veeraraghavan Basker, Christopher Nassar, Jinsheng Gao, Michael Aquilino
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Patent number: D1023725Type: GrantFiled: January 13, 2020Date of Patent: April 23, 2024Inventors: Matthias Schmolke, Daniel Meyer, Stefan Jäger