Abstract: A coupler for an automation system for controlling a process having a network interface for connection to an Ethernet-based network for receiving an Ethernet telegram having process data of the process and having control data. A local bus interface connects to a local bus for transmitting a local bus telegram. A circuit is formed between the network interface and the local bus interface. The circuit includes an arithmetic circuit for retrieving the process data from a payload data area of the Ethernet telegram. The circuit includes a first data filter circuit, which differs from the arithmetic circuit, for filtering out a predetermined subset of the control data from a header of the Ethernet telegram preceding the payload data area. The circuit is configured to generate the local bus telegram and to insert the process data and the predetermined subset of the control data into the local bus telegram.

Abstract: A coupler for an automation system for controlling a process, having a first interface for connection to a field bus for receiving a field bus message with process data of the process, a second interface for connection to a local bus for transmitting a local bus message, and a circuit implemented between the first interface and the second interface. The circuit has a non-clocked logic circuit comprising a number of hardware logic elements. The non-clocked logic circuit is equipped to change process data received through the first interface. The circuit is equipped to output the changed process data in the local bus message.

Abstract: A data bus part with a data bus interface which has a downstream data bus input for receiving data from a higher-order data bus (1), and a clock generator for generating an internal clock signal for the data bus part, is described. The data bus part has a synchronization unit to synchronize the clock generator with the clock signal of the higher-order data bus part, wherein the synchronization unit is configured to detect transitions in the downstream data stream received at the downstream data input, to regulate the frequency of the internal clock signal depending on the detected transitions, and to set a defined phasing of the internal clock signal in relation to the detected transitions.

Abstract: A data bus part (1) with a data bus interface which has a downstream data bus input (2) for receiving data from a higher-order data bus (1), and a clock generator (6) for generating an internal clock signal for the data bus part (1), is described. The data bus part (1) has a synchronization unit (7) to synchronize the clock generator (6) with the clock signal of the higher-order data bus part (1), wherein the synchronization unit (7) is configured to detect transitions in the downstream data stream (D) received at the downstream data input (2), to regulate the frequency of the internal clock signal depending on the detected transitions, and to set a defined phasing of the internal clock signal in relation to the detected transitions.