Patents by Inventor Daniel Jimenez Gonzalez

Daniel Jimenez Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11436048
    Abstract: Hardware acceleration of task dependency management in parallel computing, wherein solutions are proposed for hardware-based dependency management to support nested tasks, resolve system deadlocks as a result of memory full conditions in the dedicated hardware memory and synergetic operation of software runtime and hardware acceleration to solve otherwise unsolvable deadlocks when nested tasks are processed. Buffered asynchronous communication of larger data exchange are introduced, requiring less support from multi-core processor elements as opposed to standard access through the multi-core processor elements. A hardware acceleration processor may be implemented in the same silicon die as the multi-core processor for achieving gains in performance, fabrication cost reduction and energy consumption saving during operation.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: September 6, 2022
    Assignees: Barcelona Supercomputing Center—Centro Nacional De Supercomputacion, Universitat Politecnica De Catalunya
    Inventors: Xubin Tan, Carlos Alvarez Martinez, Jaume Bosch Pons, Daniel Jimenez Gonzalez, Mateo Valero Cortes
  • Publication number: 20200110634
    Abstract: Hardware acceleration of task dependency management in parallel computing, wherein solutions are proposed for hardware-based dependency management to support nested tasks, resolve system deadlocks as a result of memory full conditions in the dedicated hardware memory and synergetic operation of software runtime and hardware acceleration to solve otherwise unsolvable deadlocks when nested tasks are processed. Buffered asynchronous communication of larger data exchange are introduced, requiring less support from multi-core processor elements as opposed to standard access through the multi-core processor elements. A hardware acceleration processor may be implemented in the same silicon die as the multi-core processor for achieving gains in performance, fabrication cost reduction and energy consumption saving during operation.
    Type: Application
    Filed: July 24, 2017
    Publication date: April 9, 2020
    Applicants: Barcelona Supercomputing Center - Centro Nacional De Supercomputacion, Universitat Politecnica De Catalunya
    Inventors: Carlos Alvarez Martinez, Jaume Bosch Pons, Daniel Jimenez Gonzalez, Xubin Tan, Mateo Valero Cortes
  • Publication number: 20080092657
    Abstract: The invention relates to a beam former which performs coherent composition of signals originating from a given propagation direction, which are received by an array of <I>N </I> receiving transducers. The inventive methodology and devices are suitable for use in the following fields: radar, sonar, acoustic, seismology, ultrasound imaging (echography and non-destructive testing) and others. According to the invention, the beam former employs arrays having elements which can be distributed randomly. In particular, the invention can be used for dynamic focusing with deflection of the beam in azimuth and elevation, using two-dimensional arrays.
    Type: Application
    Filed: January 20, 2005
    Publication date: April 24, 2008
    Inventors: Carlos Fritsch Yusta, Montserrat Parrilla Romero, Oscar Martinez Graullera, Roberto Carlos Giacchetta, Teresa Sanchez Martin, Alberto Ibanez Rodriguez, Luis Gomez Ullate, Daniel Jimenez Gonzalez, Juan Carlos Liebana Gallego, Eugenio Villanueva Martinez