Abstract: Techniques are provided for dual port storage device emulation. A switch is configured with a first virtual switch to provide a first computing device with access a first single port device through a first port and a second port. The switch is configured with a second virtual switch to provide a second computing device with access to a second single port device through a third port and a fourth port. In response to determining that the first computing device has experienced a failure, the first virtual switch and the second virtual switch are reconfigured to provide the second computing device with access to the first single port device through the second port and access to the second single port device through the fourth port. The first computing device is disconnected from accessing the first single port device through the first virtual switch.

Abstract: Techniques are provided for dual port storage device emulation. A switch is configured with a first virtual switch to provide a first computing device with access a first single port device through a first port and a second port. The switch is configured with a second virtual switch to provide a second computing device with access to a second single port device through a third port and a fourth port. In response to determining that the first computing device has experienced a failure, the first virtual switch and the second virtual switch are reconfigured to provide the second computing device with access to the first single port device through the second port and access to the second single port device through the fourth port. The first computing device is disconnected from accessing the first single port device through the first virtual switch.

Abstract: A system and method for adaptive bus configuration operable to respond to hardware changes and other configuration changes is disclosed. In an embodiment, the computing system includes a circuit assembly having at least one processing resource coupled to a respective set of bus traces, at least one peripheral device socket coupled to a respective set of bus traces, and a bus switch coupled to the bus traces of the processing resource and the bus traces of the peripheral device. The bus switch implements a set of connections between the bus traces of the processing resource and the bus traces of the peripheral device sockets according to an instruction. The instruction may specify an allocation of peripheral device sockets to processing resources based on the number of installed processing resources so that no peripheral device is connected to a bus without an attached processor.

Abstract: A system and method for adaptive bus configuration operable to respond to hardware changes and other configuration changes is disclosed. In an embodiment, the computing system includes a circuit assembly having at least one processing resource coupled to a respective set of bus traces, at least one peripheral device socket coupled to a respective set of bus traces, and a bus switch coupled to the bus traces of the processing resource and the bus traces of the peripheral device. The bus switch implements a set of connections between the bus traces of the processing resource and the bus traces of the peripheral device sockets according to an instruction. The instruction may specify an allocation of peripheral device sockets to processing resources based on the number of installed processing resources so that no peripheral device is connected to a bus without an attached processor.

Abstract: A method and system for dynamic synchronization of a data processing system processor chips. One of a plurality of chips is designated as a primary chip and all other chips as secondary chips. The clock phase of the chips are synchronized utilizing the primary chip's clock phase as a reference clock phase for the secondary chips.

Abstract: An automated method for designing a signal distribution network in an integrated circuit confines the circuits relating to a particular signal, such as a clock signal, to multiple areas equally distributed over the integrated circuit. Each of the multiple areas have tightly-coupled logic connected to a root driver circuit in which the root driver circuit is connected to the signal input. Within the areas of tightly-coupled logic, user-defined placement circuits or groups such as a programmable clock delay having gates, delays, and splitters are connected to the root driver circuit in accordance with wire capacitance targets and input pin load balancing among all the multiple areas. The input pin load balancing and the wire capacitance targets of the user-defined placement groups connected to the root driver circuit in one of the multiple areas matches the input pin load balancing and the wire capacitance targets of other groups connected to other root driver circuits in other multiple areas.