Abstract: A light source or projector for a near-eye display includes a light source subassembly optically coupled to a waveguide concentrator. The light source subassembly may include several semiconductor chips each hosting an array of emitters such s superluminescent light-emitting diodes. The semiconductor chips may be disposed side-by-side, with their emitting sides or facets coupled to the waveguide concentrator, which provides a tight array of output light ports on a common output plane of the concentrator. The output diverging beams at the array of output light ports are coupled to a collimator, which collimates the beams and couples them to an angular scanner for scanning the collimated light beams together across the field of view of the display.

Abstract: The present disclosure relates to a power module with a power path extending through a first field-effect transistor (FET) and a second FET. A primary conductive structure connecting the first FET and the second FET in series provides a primary parasitic inductor within the power path. A first secondary conductive structure connected to both a gate and a source of the first FET provides a first secondary parasitic inductor within a first gate path, and a second secondary conductive structure connected to both a gate and a source of the second FET provides a second secondary parasitic inductor within a second gate path. The first secondary conductive structure and the second secondary conductive structure are configured such that mutual coupling between the first secondary parasitic inductor and the primary parasitic inductor and mutual coupling between the second secondary parasitic inductor and the primary parasitic inductor are substantially symmetrical.

Abstract: The present disclosure relates to a power module with a power path extending through a first field-effect transistor (FET) and a second FET. A primary conductive structure connecting the first FET and the second FET in series provides a primary parasitic inductor within the power path. A first secondary conductive structure connected to both a gate and a source of the first FET provides a first secondary parasitic inductor within a first gate path, and a second secondary conductive structure connected to both a gate and a source of the second FET provides a second secondary parasitic inductor within a second gate path. The first secondary conductive structure and the second secondary conductive structure are configured such that mutual coupling between the first secondary parasitic inductor and the primary parasitic inductor and mutual coupling between the second secondary parasitic inductor and the primary parasitic inductor are substantially symmetrical.

Abstract: A device binning and/or matching process includes measuring with a testing device currents and/or voltages of a device with respect to time, determining with the testing device binning and/or matching criteria for the device based on transfer data generated from the device currents and/or the voltages measured with respect to time, and outputting with the testing device the binning and/or matching criteria for the device. A system and power module are also disclosed.

Abstract: A device binning and/or matching process includes measuring with a testing device currents and/or voltages of a device with respect to time, determining with the testing device binning and/or matching criteria for the device based on transfer data generated from the device currents and/or the voltages measured with respect to time, and outputting with the testing device the binning and/or matching criteria for the device. A system and power module are also disclosed.

Abstract: A power module includes a power substrate, a number of power semiconductor die, and a number of connector pins. The power substrate includes a number of conductive traces. The power semiconductor die are mounted on the power substrate and electrically coupled to the conductive traces. The connector pins are each electrically coupled to a different one of the conductive traces and configured to be interconnected such that the power semiconductor die provide an active front-end and a switching power converter. By providing the power semiconductor die such that they can be interconnected to form an active front-end and a switching power converter in the same power module, the power module may provide a significantly more compact power converter system using both an active front-end and switching power converter.

Abstract: A power module includes a power substrate, a number of power semiconductor die, and a number of connector pins. The power substrate includes a number of conductive traces. The power semiconductor die are mounted on the power substrate and electrically coupled to the conductive traces. The connector pins are each electrically coupled to a different one of the conductive traces and configured to be interconnected such that the power semiconductor die provide an active front-end and a switching power converter. By providing the power semiconductor die such that they can be interconnected to form an active front-end and a switching power converter in the same power module, the power module may provide a significantly more compact power converter system using both an active front-end and switching power converter.

Abstract: A power module includes a power substrate, a number of power semiconductor die, and a number of connector pins. The power substrate includes a number of conductive traces. The power semiconductor die are mounted on the power substrate and electrically coupled to the conductive traces. The connector pins are each electrically coupled to a different one of the conductive traces and configured to be interconnected such that the power semiconductor die provide an active front-end and a switching power converter. By providing the power semiconductor die such that they can be interconnected to form an active front-end and a switching power converter in the same power module, the power module may provide a significantly more compact power converter system using both an active front-end and switching power converter.

Abstract: A device binning and/or matching process includes measuring with a testing device currents and/or voltages of a device with respect to time, determining with the testing device binning and/or matching criteria for the device based on transfer data generated from the device currents and/or the voltages measured with respect to time, and outputting with the testing device the binning and/or matching criteria for the device. A system and power module are also disclosed.