Patents by Inventor Daniel John Pelham WILKINSON

Daniel John Pelham WILKINSON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220164255
    Abstract: A system comprising: a first subsystem comprising at least one first processor, and a second subsystem comprising one or more second processors. A first program is arranged to run on the at least one first processor, the first program being configured to send data from the first subsystem to the second subsystem. A second program is arranged to run on the one more second processors, the second program being configured to operate on the data content from the first subsystem. The first program is configured to set a checkpoint at one or more points in time. At each checkpoint it records in memory of the first subsystem i) a program state of the second program, comprising a state of one or more registers on each of the second processors at the time of the checkpoint, and ii) a copy of the data content sent to the second subsystem since the respective checkpoint.
    Type: Application
    Filed: February 14, 2022
    Publication date: May 26, 2022
    Inventors: David Lacey, Daniel John Pelham WILKINSON
  • Patent number: 11334400
    Abstract: A gateway implementing multiple independent sync networks. The independent sync networks can be used to allow for synchronisation between different synchronisation groups of accelerators. The independent sync networks allow synchronisations to be carried out asynchronously and simultaneously. The gateway has sync propagation circuitry that receives a first synchronisation request for an upcoming exchange phase and propagates this sync request through a first sync network. The first synchronisation request is a request for synchronisation between subsystems of a first synchronisation group. The sync propagation circuitry of the gateway also receives a second synchronisation request for a different exchange phase and propagates this sync request through the second sync network. The second synchronisation request is a request for synchronisation between subsystems of a second synchronisation group. The two exchange phases overlap in time. Therefore, the syncs are simultaneous and asynchronous.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: May 17, 2022
    Assignee: GRAPHCORE LIMITED
    Inventors: Brian Manula, Daniel John Pelham Wilkinson
  • Patent number: 11327813
    Abstract: Implicit sync group selection is performed by having dual interfaces to a gateway. A subsystem coupled to the gateway selects a sync group to be used for an upcoming exchange by selecting the interface to which a sync request is written to. The gateway propagates the sync requests and/or acknowledgments in dependence upon configuration settings for the sync group that is associated with the interface to which the sync request was written to.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: May 10, 2022
    Assignee: GRAPHCORE LIMITED
    Inventors: Brian Manula, Daniel John Pelham Wilkinson
  • Patent number: 11321272
    Abstract: The invention relates to a computer program comprising a sequence of instructions for execution on a processing unit having instruction storage for holding the computer program, an execution unit for executing the computer program and data storage for holding data, the computer program comprising one or more computer executable instruction which, when executed, implements: a send function which causes a data packet destined for a recipient processing unit to be transmitted on a set of connection wires connected to the processing unit, the data packet having no destination identifier but being transmitted at a predetermined transmit time; and a switch control function which causes the processing unit to control switching circuitry to connect a set of connection wires of the processing unit to a switching fabric to receive a data packet at a predetermined receive time.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: May 3, 2022
    Assignee: Graphcore Limited
    Inventors: Simon Christian Knowles, Daniel John Pelham Wilkinson, Richard Luke Southwell Osborne, Alan Graham Alexander, Stephen Felix, Jonathan Mangnall, David Lacey
  • Patent number: 11263081
    Abstract: A system comprising: a first subsystem comprising at least one first processor, and a second subsystem comprising one or more second processors. A first program is arranged to run on the at least one first processor, the first program being configured to send data from the first subsystem to the second subsystem. A second program is arranged to run on the one more second processors, the second program being configured to operate on the data content from the first subsystem. The first program is configured to set a checkpoint at successive points in time. At each checkpoint it records in memory of the first subsystem i) a program state of the second program, comprising a state of one or more registers on each of the second processors at the time of the checkpoint, and ii) a copy of the data content sent to the second subsystem since the respective checkpoint.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: March 1, 2022
    Assignee: Graphcore Limited
    Inventors: David Lacey, Daniel John Pelham Wilkinson
  • Patent number: 11262787
    Abstract: The invention relates to a computer implemented method of generating multiple programs to deliver a computerised function, each program to be executed in a processing unit of a computer comprising a plurality of processing units each having instruction storage for holding a local program, an execution unit for executing the local program and data storage for holding data, a switching fabric connected to an output interface of each processing unit and connectable to an input interface of each processing unit by switching circuitry controllable by each processing unit, and a synchronisation module operable to generate a synchronisation signal, the method comprising: generating a local program for each processing unit comprising a sequence of executable instructions; determining for each processing unit a relative time of execution of instructions of each local program whereby a local program allocated to one processing unit is scheduled to execute with a predetermined delay relative to a synchronisation signal
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 1, 2022
    Assignee: GRAPHCORE LIMITED
    Inventors: Simon Christian Knowles, Daniel John Pelham Wilkinson, Richard Luke Southwell Osborne, Alan Graham Alexander, Stephen Felix, Jonathan Mangnall, David Lacey
  • Publication number: 20220050494
    Abstract: A predictive clock controller is provided for modifying the frequency of a clock signal provided to a processing unit based on knowledge of the power usage by the application running on the processing unit during different execution periods. The predictive clock controller counts barrier syncs for the application, so as to determine where the application is in its sync schedule. The predictive clock controller is able to determine from the number of counted syncs, when the application will transition from one execution period to another execution period with different power requirements, and to adjust the clock frequency accordingly.
    Type: Application
    Filed: June 30, 2021
    Publication date: February 17, 2022
    Inventors: Owain JONES, Daniel John Pelham WILKINSON
  • Patent number: 11237882
    Abstract: A gateway for interfacing a host with a subsystem for acting as a work accelerator to the host. The gateway enables the transfer of batches of data to the subsystem at precompiled data exchange synchronisation points. The gateway comprises a streaming engine having a data mover engine and a memory management engine, the data mover engine and memory management engine being configured to execute instructions in coordination from work descriptors. The memory management engine is configured to execute instructions from the work descriptor to transfer data between external storage and the local memory associated with the gateway. The data mover engine is configured to execute instructions from the work descriptor to transfer data between the local memory associated with the gateway and the subsystem.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 1, 2022
    Assignee: Graphcore Limited
    Inventors: Ola Tørudbakken, Daniel John Pelham Wilkinson, Richard Luke Southwell Osborne, Brian Manula, Harald Høeg
  • Publication number: 20220019668
    Abstract: A new apparatus and method for securely distributing an application to processors of a processing unit. The processing unit is formed as part of an integrated circuit and comprises a plurality of processors (referred to as tiles), each having their own execution unit and storage for storing application data and additional executable instructions. The integrated circuit comprises a hardware module (referred to herein as the autoloader) that is configured to distribute a set of bootloader instructions (referred to herein as a secondary bootloader) to each of at least some of the tiles. Each of the tiles then executes instructions of the received secondary bootloader, which causes each tile to issue read requests to read a set of executable application instructions from a memory external to the integrated circuit. Each tile then performs operations using the received set of executable application instructions so as execute the application using the processing unit.
    Type: Application
    Filed: June 4, 2021
    Publication date: January 20, 2022
    Inventor: Daniel John Pelham WILKINSON
  • Publication number: 20220021512
    Abstract: An apparatus is provided for converting the form in which a synchronisation request for a barrier synchronisation is provided. The synchronisation request is provided from a first synchronisation circuitry to a second synchronisation circuitry by asserting one of a set of separate signals that may each correspond to a bit in a register or a signal on a wire. The second synchronisation circuitry provides for the packetisation of the sync request by sending a packet comprising the sync request over a network to be received at a further subsystem.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 20, 2022
    Inventors: Martin VICKERS, Daniel John Pelham WILKINSON
  • Publication number: 20220019552
    Abstract: A processor in a network has a plurality of processing units arranged on a chip. An on-chip interconnect enables data to be exchanged between the processing units. A plurality of external interfaces are configured to communicate data off chip in the form of packets, each packet having a destination address identifying a destination of the packet. The external interfaces are connected to respective additional connected processors. A routing bus routes packets between the processing units and the external interfaces. A routing register defines a routing domain for the processor, the routing domain comprising one or more of the additional processor, and at least a subset of further additional processors of the network, wherein the additional processors of the subset are directly or indirectly connected to the processor. The routing domain can be modified by changing the contents of the routing register as a sliding window domain.
    Type: Application
    Filed: July 13, 2021
    Publication date: January 20, 2022
    Inventors: Daniel John Pelham WILKINSON, Lars Paul HUSE, Richard Luke Southwell OSBORNE, Graham Bernard CUNNINGHAM, Hachem YASSINE
  • Publication number: 20220019700
    Abstract: A system and method for encrypting and decrypting data exchanged between a multi-tile processing unit and a storage, where a plurality of keys are used for the encryption. Each of the plurality of keys is associated with a different one or more sets of the processors. Encryption hardware is configured to select a key to use for encryption/decryption operations in dependence upon the set of tiles associated with the data being exchanged. Each write request from a tile contains identifier bits associated with that tile's set of tiles, enabling the encryption hardware to select the key to use for encrypting the data in the write request. Each read completion for a tile contains identifier bits associated with that tile's set of tiles, enabling the encryption hardware to select the key to use for decrypting the data in the read completion.
    Type: Application
    Filed: July 13, 2021
    Publication date: January 20, 2022
    Inventors: Daniel John Pelham WILKINSON, Graham Bernard CUNNINGHAM, Stavros VOLOS, Kapil VASWANI, Cedric Alain Marie FOURNET, Balaji VEMBU
  • Publication number: 20210397572
    Abstract: A device comprising: a control bus; a plurality of requesting circuits each accessible on the control bus, wherein each of the plurality of requesting circuits is operable to dispatch read or write requests to the control bus for delivery to at least one of a plurality of receiving circuits, and the plurality of receiving circuits each accessible on the control bus, and each of which is operable to receive requests from the at least one control bus and service the requests by providing at least one of read or write access to storage associated with the respective receiving circuit, wherein the control bus provides a ring path configured to support, the requests in circulation in the ring path, wherein the control bus is configured to propagate each of at least some of the requests at least until those requests have been serviced by at least one of the receiving circuits.
    Type: Application
    Filed: May 24, 2021
    Publication date: December 23, 2021
    Inventors: Graham Bernard CUNNINGHAM, Daniel John Pelham WILKINSON
  • Publication number: 20210397754
    Abstract: Access permissions are set for different requesting circuits on a control bus. The access permissions can be set by the level 1 manager and the level 2 manager, allowing two layers of security to be added. The level 1 manager has priority, allowing it to add access permissions that cannot be removed by the level 2 manager.
    Type: Application
    Filed: May 24, 2021
    Publication date: December 23, 2021
    Inventors: Daniel John Pelham WILKINSON, Graham Bernard CUNNINGHAM
  • Publication number: 20210342492
    Abstract: A peripheral device, for use with a host, comprises one or more compute elements a security module and at least one encryption unit. The security module is configured to form a trusted execution environment on the peripheral device for processing sensitive data using sensitive code. The sensitive data and sensitive code are provided by a trusted computing entity which is in communication with the host computing device. The at least one encryption unit is configured to encrypt and decrypt data transferred between the trusted execution environment and the trusted computing entity via the host computing device. The security module is configured to compute and send an attestation to the trusted computing entity to attest that the sensitive code is in the trusted execution environment.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 4, 2021
    Inventors: Stavros VOLOS, David Thomas CHISNALL, Saurabh Mohan KULKARNI, Kapil VASWANI, Manuel COSTA, Samuel Alexander WEBSTER, Cédric Alain Marie FOURNET, Richard OSBORNE, Daniel John Pelham WILKINSON, Graham Bernard CUNNINGHAM
  • Publication number: 20210271527
    Abstract: A processing system comprising an arrangement of tiles and an interconnect between the tiles. The interconnect comprises synchronization logic for coordinating a barrier synchronization to be performed between a group of the tiles. The instruction set comprises a synchronization instruction taking an operand which selects one of a plurality of available modes each specifying a different membership of the group. Execution of the synchronization instruction cause a synchronization request to be transmitted from the respective tile to the synchronization logic, and instruction issue to be suspended on the respective tile pending a synchronization acknowledgement being received back from the synchronization logic. In response to receiving the synchronization request from all the tiles in the group as specified by the operand of the synchronization instruction, the synchronization logic returns the synchronization acknowledgment to the tiles in the specified group.
    Type: Application
    Filed: May 14, 2021
    Publication date: September 2, 2021
    Inventors: Daniel John Pelham Wilkinson, Simon Christian Knowles, Matthew David Fyles, Alan Graham Alexander, Stephen Felix
  • Patent number: 11106510
    Abstract: A processing system comprising: a subsystem for acting as a work accelerator to a host processor, the subsystem comprising an arrangement of tiles; and an interconnect for communicating between the tiles and connecting the subsystem to the host. The interconnect comprises synchronization logic to coordinate barrier synchronizations between a group of the tiles. The synchronization logic comprises a host sync proxy module, comprising a counter written with a number of credits by the host processor, and being configured to automatically decrement the number of credits each time one of the barrier synchronizations requiring host involvement is performed. When the number of credits in the counter is exhausted, the barrier is not released until a further write from the host to the host sync proxy module, but when the number is credits in the counter is not exhausted the barrier is released without a separate write from the host.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 31, 2021
    Assignee: GRAPHCORE LIMITED
    Inventors: Daniel John Pelham Wilkinson, Stephen Felix, Matthew David Fyles, Richard Luke Southwell Osborne
  • Publication number: 20210200602
    Abstract: A gateway implementing multiple independent sync networks. The independent sync networks can be used to allow for synchronisation between different synchronisation groups of accelerators. The independent sync networks allow synchronisations to be carried out asynchronously and simultaneously. The gateway has sync propagation circuitry that receives a first synchronisation request for an upcoming exchange phase and propagates this sync request through a first sync network. The first synchronisation request is a request for synchronisation between subsystems of a first synchronisation group. The sync propagation circuitry of the gateway also receives a second synchronisation request for a different exchange phase and propagates this sync request through the second sync network. The second synchronisation request is a request for synchronisation between subsystems of a second synchronisation group. The two exchange phases overlap in time. Therefore, the syncs are simultaneous and asynchronous.
    Type: Application
    Filed: December 17, 2020
    Publication date: July 1, 2021
    Inventors: Brian MANULA, Daniel John Pelham WILKINSON
  • Publication number: 20210200601
    Abstract: Implicit sync group selection is performed by having dual interfaces to a gateway. A subsystem coupled to the gateway selects a sync group to be used for an upcoming exchange by selecting the interface to which a sync request is written to. The gateway propagates the sync requests and/or acknowledgments in dependence upon configuration settings for the sync group that is associated with the interface to which the sync request was written to.
    Type: Application
    Filed: December 17, 2020
    Publication date: July 1, 2021
    Inventors: Brian MANULA, Daniel John Pelham WILKINSON
  • Patent number: 11048563
    Abstract: A processing system comprising: a subsystem for acting as a work accelerator to a host processor, the subsystem comprising an arrangement of tiles; and an interconnect for communicating between the tiles and connecting the subsystem to the host. The interconnect comprises synchronization logic to coordinate barrier synchronizations between a group of the tiles. The synchronization logic comprises a host sync proxy module, comprising a counter written with a number of credits by the host processor, and being configured to automatically decrement the number of credits each time one of the barrier synchronizations requiring host involvement is performed. When the number of credits in the counter is exhausted, the barrier is not released until a further write from the host to the host sync proxy module, but when the number is credits in the counter is not exhausted the barrier is released without a separate write from the host.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 29, 2021
    Assignee: Graphcore Limited
    Inventors: Daniel John Pelham Wilkinson, Stephen Felix, Matthew David Fyles, Richard Luke Southwell Osborne