Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

Abstract: Latch-based multiply-accumulate (MAC) operations implemented on the die of a non-volatile memory (NVM) array are disclosed. The exemplary latch-based MAC procedures described herein are linear procedures that do not require logic branches. In one example, the MAC operation uses a set of linear MAC stages, wherein each linear stage processes MAC operations corresponding to one bit of a first multi-bit multiplicand being multiplied against a second multi-bit multiplicand. Examples are provided wherein the MAC procedures are performed as part of a neural network feedforward procedure where the first multiplicand is a synaptic weight and the second multiplicand is an activation value. Multiple plane and multiple die NVM array implementations are also described for massive parallel processing.

Abstract: Latch-based methods and apparatus for performing neural network weight parity detection on the die of a non-volatile memory (NVM) array to detect bit flip errors within neural network weight data are described, particularly for use with floating point number values. Upon detection of a parity error in a neural network weight, the erroneous weight is set to zero to trim the corresponding neuron from the network, thus preventing the erroneous value from significantly affecting the network, particularly in situations where the bit flip would otherwise affect the magnitude of a floating-point weight value. The exemplary latch-based procedures described herein are linear procedures that do not require logic decisions. Procedures are also described that assess an amount of degradation in the NVM array based on parity bit data collected in the latches. Multiple plane and multiple die NVM array implementations are also described for massive parallel processing.

Abstract: Bit-flip object insertion techniques are provided for use with a non-volatile memory (NVM) wherein an object is inserted into a background image by flipping or inverting one or more bits within the pixels of the background image that correspond to the shape and insertion location of an object being inserted. In an illustrative example, pixels within the background image that correspond to the shape and insertion location of the object are XORed with binary 1s. This flips the bits of those pixels to change the color (hue) and/or intensity (brightness) of the pixels so the object appears in the background image. In other examples, only the most significant bits of pixels in the background image are inverted (flipped). Exemplary latch-based procedures are described herein for high-speed processing on an NVM die. Multiple plane NVM die implementations are also described for massive processing.

Abstract: Noise injection procedures implemented on the die of a non-volatile memory (NVM) array are disclosed. In one example, noise is injected into data by adjusting read voltages to induce bit flips while using feedback to achieve a target amount of information degradation. In another example, random data is iteratively combined with itself to achieve a target percentage of random 1s or 0s, then the random data is combined with data read from the NVM array. In other examples, pixels are randomly zeroed out to emulate dead charge coupled device (CCD) pixels. In still other examples, the timing, voltage, and/or current values used within circuits while transferring data to/from latches or bitlines are adjusted outside their specified margins to induce bit flips to inject noise into the data. The noise-injected data may be used, for example, for dataset augmentation or for the testing of deep neural networks (DNNs).

Abstract: Noise injection procedures implemented on the die of a non-volatile memory (NVM) array are disclosed. In one example, noise is injected into data by adjusting read voltages to induce bit flips while using feedback to achieve a target amount of information degradation. In another example, random data is iteratively combined with itself to achieve a target percentage of random 1s or 0s, then the random data is combined with data read from the NVM array. In other examples, pixels are randomly zeroed out to emulate dead charge coupled device (CCD) pixels. In still other examples, the timing, voltage, and/or current values used within circuits while transferring data to/from latches or bitlines are adjusted outside their specified margins to induce bit flips to inject noise into the data. The noise-injected data may be used, for example, for dataset augmentation or for the testing of deep neural networks (DNNs).

Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

Abstract: A first entropy indicator is calculated at a first time for a collection of data stored in at least one memory. A second entropy indicator is calculated at a second time for the collection of data. The first entropy indicator is compared with the second entropy indicator. Based on the comparison, it is determined whether to back up the collection of data and/or whether to retain an earlier backup of the collection of data.

Abstract: A Data Storage Device (DSD) or a server is set to an unlocked state to allow access to a memory of the DSD or to a DSD of the server. Communication is established with an access station using a wireless communication interface, and an access code is received from the access station via the wireless communication interface. If the received access code is determined to be valid, the DSD or server is set to the unlocked state. According to another aspect, communication is established with a DSD or a server using a wireless communication interface, and an access code is generated and sent to the DSD or the server for setting the DSD or the server to the unlocked state.

Abstract: Aspects of the disclosure provide for reducing a temperature of one or more non-volatile memory (NVM) dies of a solid state drive (SSD). The methods and apparatus detect a temperature of one or more NVM dies of a plurality of NVM dies of the SSD, the plurality of NVM dies including at least one parity NVM die, and determine that the one or more NVM dies is overheated when the detected temperature is at or above a threshold temperature. If the detected temperature is at or above the threshold temperature, the methods and apparatus redirect parity data designated for the at least one parity NVM die to the one or more overheated NVM dies. By repurposing the one more overheated NVM dies to store the parity data, the repurposed dies will experience less activity, and therefore, generate less heat without throttling or reducing the workload capability of the dies.

Abstract: Aspects of the disclosure provide for reducing a temperature of one or more non-volatile memory (NVM) dies of a solid state drive (SSD). The methods and apparatus detect a temperature of one or more NVM dies of a plurality of NVM dies of the SSD, the plurality of NVM dies including at least one parity NVM die, and determine that the one or more NVM dies is overheated when the detected temperature is at or above a threshold temperature. If the detected temperature is at or above the threshold temperature, the methods and apparatus redirect parity data designated for the at least one parity NVM die to the one or more overheated NVM dies. By repurposing the one more overheated NVM dies to store the parity data, the repurposed dies will experience less activity, and therefore, generate less heat without throttling or reducing the workload capability of the dies.

Abstract: A first entropy indicator is calculated at a first time for a collection of data stored in at least one memory. A second entropy indicator is calculated at a second time for the collection of data. The first entropy indicator is compared with the second entropy indicator. Based on the comparison, it is determined whether to back up the collection of data and/or whether to retain an earlier backup of the collection of data.

Abstract: A Data Storage Device (DSD) or a server is set to an unlocked state to allow access to a memory of the DSD or to a DSD of the server. Communication is established with an access station using a wireless communication interface, and an access code is received from the access station via the wireless communication interface. If the received access code is determined to be valid, the DSD or server is set to the unlocked state. According to another aspect, communication is established with a DSD or a server using a wireless communication interface, and an access code is generated and sent to the DSD or the server for setting the DSD or the server to the unlocked state.

Abstract: Certain apparatuses, systems, methods, and computer program products are used for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

Abstract: Techniques are presented for the prevention and detection of inter-plane disturbs in a memory circuit, where, when concurrently performing memory operations on multiple planes, a defect in one plane can feed back through a common supply node and adversely affect memory operations in another node. To isolate such defects to plane in which the occur, the memory supplies the elements, such as a word line, of different planes from a common supply node through a uni-directional circuit element, such as a diode. In this way, if the voltage on an element in an array gets pulled up to an elevated voltage though a defect, this elevated voltage is stopped from flowing back to the common supply node. Additionally, by comparing the voltage levels on either side of the uni-directional circuit element, it can be determined whether such a defect is present in an array.

Abstract: Techniques are presented for the prevention and detection of inter-plane disturbs in a memory circuit, where, when concurrently performing memory operations on multiple planes, a defect in one plane can feed back through a common supply node and adversely affect memory operations in another node. To isolate such defects to plane in which the occur, the memory supplies the elements, such as a word line, of different planes from a common supply node through a uni-directional circuit element, such as a diode. In this way, if the voltage on an element in an array gets pulled up to an elevated voltage though a defect, this elevated voltage is stopped from flowing back to the common supply node. Additionally, by comparing the voltage levels on either side of the uni-directional circuit element, it can be determined whether such a defect is present in an array.