Abstract: A system is described for connecting a printed circuit board (PCB) under test to a digital analysis unit to permit verification of the functional behavior of the PCB. A bed-of-nails (BON) fixture is employed, allowing access to internal circuit nodes of the PCB. Controlled-impedance wiring, terminated in its characteristic impedance at the test electronics, allows high speed signals to be communicated without degradation from the unit under test (UUT). Excessive dynamic loading of the UUT circuit nodes is avoided by employing isolation resistance at each BON probe. The potentially large number of UUT signals to be monitored is multiplexed down to a smaller number of lines more readily accommodated by the digital analysis unit. The selected signals from the UUT are processed in a wide-band asynchronous manner by the test electronics in such a way that uniform delay of all signals through the multiplexer is achieved.

Abstract: An interface between a microprocessor chip and input/output, and memory modules. The interface uses a single, bidirectional bus comprised of a number of lines which is less than the number necessary to carry a complete address word or a full width data word. Information transfer is effected by transferring information in small portions utilizing two or more interface clock cycles. An encoded control specification placed on the bus during the first cycle of information transfer specifies the type of access, the direction of transfer, and the length (number of bytes) of data to be moved. Only two additional simplex lines, one from the microprocessor and the other to the microprocessor are needed to complete the basic interface.

Abstract: Method and circuit for checking integrated circuit chips without the use of external checking circuits. Chips are fabricated with an error-checking circuit on each chip. Data from data processing logic on each chip is outputted via a first path to one input of its respective checking circuit and via a second path to an output pin or pins. The output pin on each chip is also connected via a third path to the other input of its checking circuit. The input and output pins of each chip are wired in parallel. A separate check input pin is provided to each integrated circuit chip. On one chip this pin is activated, making this first chip the checker. On the other chip, the check input pin is deactivated. On the chip which is the checker, the output from the data processing logic is prevented from being passed externally via the first path, but is allowed to enter the checking circuit via the second path.