Abstract: The present disclosure includes switched capacitor transmitter circuits and methods. In one embodiment, the present disclosure includes a plurality of switched capacitor transmitter circuits coupled to inputs of an inductive network. The inductive network combines voltages from the switched capacitor transmitter circuits to produce a combined voltage on an output. In another embodiment, a digital data signal is thermometer encoded and a negative thermo-encoded signal is bit order reversed to control capacitors in a switched capacitor transmitter circuit.

Abstract: The present disclosure includes switched capacitor transmitter circuits and methods. In one embodiment, a digital data signal is thermometer encoded and a negative thermo-encoded signal is bit order reversed to control capacitors in a switched capacitor transmitter circuit. In another embodiment, the present disclosure includes a plurality of switched capacitor transmitter circuits coupled to inputs of an inductive network. The inductive network combines voltages from the switched capacitor transmitter circuits to produce a combined voltage on an output.

Abstract: The present disclosure includes switched capacitor transmitter circuits and methods. In one embodiment, the present disclosure includes a plurality of switched capacitor transmitter circuits coupled to inputs of an inductive network. The inductive network combines voltages from the switched capacitor transmitter circuits to produce a combined voltage on an output. In another embodiment, a digital data signal is thermometer encoded and a negative thermo-encoded signal is bit order reversed to control capacitors in a switched capacitor transmitter circuit.

Abstract: The present disclosure includes switched capacitor transmitter circuits and methods. In one embodiment, a digital data signal is thermometer encoded and a negative thermo-encoded signal is bit order reversed to control capacitors in a switched capacitor transmitter circuit. In another embodiment, the present disclosure includes a plurality of switched capacitor transmitter circuits coupled to inputs of an inductive network. The inductive network combines voltages from the switched capacitor transmitter circuits to produce a combined voltage on an output.

Abstract: A transmitter includes a delta-sigma modulator characterized by a noise transfer function having a multitude of zeroes positioned substantially near a frequency band of a receive signal. The transmitter further includes, in part, a multi-phase digital-to-analog (DAC) converter converting an output signal of the delta-sigma modulator to an analog signal. The DAC is characterized by a transfer function that passes the desired signal to its output and attenuates a multitude of images of the sampling clock signal. The transmitter transmits at a frequency defined by an odd multiple of a fraction of the sampling clock signal frequency. The DAC includes a number of stages each pair of which is associated with one of the images being attenuated. The delta-sigma modulator includes a multitude of stages each associated with a different one of the zeroes. Each stage of said delta-sigma modulator optionally receives three tap coefficients.

Abstract: An apparatus and method for communications are disclosed. The apparatus may include an a quantizer having three levels, and a switching power amplifier configured to drive a load having first and second terminals, wherein the switching power amplifier is further configured to switch the first and second terminals between first and second power rails only if the output from the quantizer is at one of the three levels.

Abstract: An apparatus and method for communications are disclosed. The apparatus may include an a quantizer having three levels, and a switching power amplifier configured to drive a load having first and second terminals, wherein the switching power amplifier is further configured to switch the first and second terminals between first and second power rails only if the output from the quantizer is at one of the three levels.

Abstract: An apparatus and method for communications are disclosed. The apparatus may include an a quantizer having three levels, and a switching power amplifier configured to drive a load having first and second terminals, wherein the switching power amplifier is further configured to switch the first and second terminals between first and second power rails only if the output from the quantizer is at one of the three levels.

Abstract: An apparatus and method for communications are disclosed. The apparatus may include an a quantizer having three levels, and a switching power amplifier configured to drive a load having first and second terminals, wherein the switching power amplifier is further configured to switch the first and second terminals between first and second power rails only if the output from the quantizer is at one of the three levels.

Abstract: A hardware-efficient transceiver. The transceiver includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal A digital-to-analog converter converts the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal. In the transceiver implementation, the digital circuit upconverts a first transmit signal from a first frequency to a second frequency in response to the second periodic signal and provides a digital transmit signal in response thereto. A second circuit is provided for converting the digital transmit signal to an analog transmit signal.

Abstract: An inventive high-resolution Delta-Sigma analog-to-digital converter using a Continuous-Time implementation having suppressed sensitivity to clock jitter. The inventive method and apparatus suppresses the sensitivity to jitter by the square of the oversampling ratio when compared to current Continuous-Time implementations of Delta-Sigma modulators. The present invention eliminates the clock jitter disadvantage between sampled-data and Continuous-Time implementations of Delta-Sigma modulators. The present invention preferably includes a digital-to-analog converter that ensures that the integral of an output voltage is constant over a clock duty cycle regardless of clock jitter. The digital-to-analog converter preferably includes at least two switches and a capacitor. A first switch is used to charge the capacitor and a second switch is used to discharge the capacitor. Each switch is controlled by a clock phase wherein the sum of the two phases equals the clock duty cycle.