Patents by Inventor Daniel KHANKIN
Daniel KHANKIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12625678Abstract: A method of computing logarithms, comprising receiving a number, computing an exponent and significand of the received number, selecting a breakpoint value from a plurality of breakpoint values segmenting a range of the significand wherein the selected breakpoint value is the significand's greatest lower bound or lowest upper bound, computing a multiplication of the exponent and a logarithm value of two, computing a first intermediate value based on a least significant portion of the significand and an inverse value of the selected breakpoint value, computing an approximated logarithm value of a second intermediate value derived from the first intermediate value, computing a logarithm value of the significand by summing the approximated logarithm value and a logarithm value of the selected breakpoint value, computing a logarithm value of the received number by summing the logarithm value of the significand and the multiplication of the exponent and the logarithm value of two.Type: GrantFiled: February 14, 2024Date of Patent: May 12, 2026Assignee: Next Silicon LtdInventors: Daniel Khankin, Tomer Levin, Daniel Srebnik
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Publication number: 20260086909Abstract: An apparatus for computing functions using polynomial-based approximation, comprising one or more processing circuitries configured for computing a polynomial-based approximant approximating a function by executing one or more iterations. Each iteration comprising computing the polynomial-based approximant using scaled fixed-point unit(s) according to a constructed set of coefficients, minimizing an approximation error of the computed polynomial-based approximant compared to the function while complying with one or more constraints selected from a group comprising at least: an accuracy, a compute graph size, a computation complexity, and a hardware utilization of the processing circuitry(s), adjusting one or more of the coefficients in case the approximation error is incompliant with the constraint(s) and initiating another iteration.Type: ApplicationFiled: November 27, 2025Publication date: March 26, 2026Applicant: Next Silicon LtdInventor: Daniel KHANKIN
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Patent number: 12536248Abstract: An integrated circuit (IC) for computing an output value Y1 of a mathematical function, for a given input value X1, defined over an approximation interval I1, may include: (i) a look-up table (LUT) circuit with multiple entries, each corresponding to a segment of I1, (ii) a polynomial computation circuit configured to calculate a polynomial estimation of the function in a reference segment, and (iii) a processor. The processor may obtain a query for computing Y1 and select a segment based on X1. It may retrieve a preliminary approximation of Y1 from the LUT and calculate an offset of X1 within the selected segment. The processor may employ the polynomial computation circuit to calculate a polynomial estimation on the offset value, thereby obtaining a correction value. The processor may proceed to compute Y1 based on the preliminary approximation and the correction value.Type: GrantFiled: February 19, 2025Date of Patent: January 27, 2026Assignee: Next Silicon LtdInventors: Daniel Khankin, Aharon Abadi
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Patent number: 12487903Abstract: An apparatus for computing functions using polynomial-based approximation, comprising one or more processing circuitries configured for computing a polynomial-based approximant approximating a function by executing one or more iterations. Each iteration comprising computing the polynomial-based approximant using scaled fixed-point unit(s) according to a constructed set of coefficients, minimizing an approximation error of the computed polynomial-based approximant compared to the function while complying with one or more constraints selected from a group comprising at least: an accuracy, a compute graph size, a computation complexity, and a hardware utilization of the processing circuitry(s), adjusting one or more of the coefficients in case the approximation error is incompliant with the constraint(s) and initiating another iteration.Type: GrantFiled: May 2, 2024Date of Patent: December 2, 2025Assignee: Next Silicon LtdInventor: Daniel Khankin
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Publication number: 20250258649Abstract: A method of computing logarithms, comprising receiving a number, computing an exponent and significand of the received number, selecting a breakpoint value from a plurality of breakpoint values segmenting a range of the significand wherein the selected breakpoint value is the significand's greatest lower bound or lowest upper bound, computing a multiplication of the exponent and a logarithm value of two, computing a first intermediate value based on a least significant portion of the significand and an inverse value of the selected breakpoint value, computing an approximated logarithm value of a second intermediate value derived from the first intermediate value, computing a logarithm value of the significand by summing the approximated logarithm value and a logarithm value of the selected breakpoint value, computing a logarithm value of the received number by summing the logarithm value of the significand and the multiplication of the exponent and the logarithm value of two.Type: ApplicationFiled: February 14, 2024Publication date: August 14, 2025Applicant: Next Silicon LtdInventors: Daniel KHANKIN, Tomer LEVIN, Daniel SREBNIK
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Publication number: 20250252037Abstract: A method of generating automatically architecture-specific algorithms, comprising receiving an architecture independent algorithm and one or more algorithm parameters defining at least a target processing architecture and a format of an output of an architecture-specific algorithm implementing the received algorithm, determining automatically a functionality of the algorithm by analyzing the algorithm, selecting one or more architecture-specific computing blocks of the target processing architecture according to the functionality of the algorithm and the algorithm parameter(s) wherein each computing block is dynamically reconfigurable in runtime and associated with (1) simulation code simulating its functionality, and (2) execution code executing its functionality, testing an emulated architecture-specific algorithm constructed using the simulation code of the selected architecture-specific computing block(s) to verify compliance with the algorithm parameter(s), and, responsive to successful compliance verifiType: ApplicationFiled: April 11, 2025Publication date: August 7, 2025Applicant: Next Silicon LtdInventor: Daniel KHANKIN
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Patent number: 12277051Abstract: A method of generating automatically architecture-specific algorithms, comprising receiving an architecture independent algorithm and one or more algorithm parameters defining at least a target processing architecture and a format of an output of an architecture-specific algorithm implementing the received algorithm, determining automatically a functionality of the algorithm by analyzing the algorithm, selecting one or more architecture-specific computing blocks of the target processing architecture according to the functionality of the algorithm and the algorithm parameter(s) wherein each computing block is dynamically reconfigurable in runtime and associated with (1) simulation code simulating its functionality, and (2) execution code executing its functionality, testing an emulated architecture-specific algorithm constructed using the simulation code of the selected architecture-specific computing block(s) to verify compliance with the algorithm parameter(s), and, responsive to successful compliance verifiType: GrantFiled: February 5, 2024Date of Patent: April 15, 2025Assignee: Next Silicon LtdInventor: Daniel Khankin
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Publication number: 20240289248Abstract: An apparatus for computing functions using polynomial-based approximation, comprising one or more processing circuitries configured for computing a polynomial-based approximant approximating a function by executing one or more iterations. Each iteration comprising computing the polynomial-based approximant using scaled fixed-point unit(s) according to a constructed set of coefficients, minimizing an approximation error of the computed polynomial-based approximant compared to the function while complying with one or more constraints selected from a group comprising at least: an accuracy, a compute graph size, a computation complexity, and a hardware utilization of the processing circuitry(s), adjusting one or more of the coefficients in case the approximation error is incompliant with the constraint(s) and initiating another iteration.Type: ApplicationFiled: May 2, 2024Publication date: August 29, 2024Applicant: Next Silicon LtdInventor: Daniel KHANKIN
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Patent number: 12001311Abstract: An apparatus for computing functions using polynomial-based approximation, comprising one or more processing circuitries configured for computing a polynomial-based approximant approximating a function by executing one or more iterations. Each iteration comprising computing the polynomial-based approximant using scaled fixed-point unit(s) according to a constructed set of coefficients, minimizing an approximation error of the computed polynomial-based approximant compared to the function while complying with one or more constraints selected from a group comprising at least: an accuracy, a compute graph size, a computation complexity, and a hardware utilization of the processing circuitry(s), adjusting one or more of the coefficients in case the approximation error is incompliant with the constraint(s) and initiating another iteration.Type: GrantFiled: January 6, 2022Date of Patent: June 4, 2024Assignee: Next Silicon LtdInventor: Daniel Khankin
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Publication number: 20230214307Abstract: An apparatus for computing functions using polynomial-based approximation, comprising one or more processing circuitries configured for computing a polynomial-based approximant approximating a function by executing one or more iterations. Each iteration comprising computing the polynomial-based approximant using scaled fixed-point unit(s) according to a constructed set of coefficients, minimizing an approximation error of the computed polynomial-based approximant compared to the function while complying with one or more constraints selected from a group comprising at least: an accuracy, a compute graph size, a computation complexity, and a hardware utilization of the processing circuitry(s), adjusting one or more of the coefficients in case the approximation error is incompliant with the constraint(s) and initiating another iteration.Type: ApplicationFiled: January 6, 2022Publication date: July 6, 2023Applicant: Next Silicon LtdInventor: Daniel KHANKIN