Abstract: The present disclosure generally relates to improving the accuracy of autonomous vehicle simulations by identifying which test results are most dependent on a hardware type and/or software version used in the computing systems of the simulation and the AV. In some aspects, a method of the disclosed technology includes steps for performing a test on a first hardware component type associated with an AV to produce a first output; performing the test on a second hardware component type associated with a simulation of an AV to produce a second output; comparing the first output with the second output using a statistical analysis to determine a value related to a difference between the first output and the second output; and assigning a weight to the test based on the value related to the difference between the first output and the second output. Systems and machine-readable media are also provided.

Abstract: Methods, systems, and apparatus, including an apparatus for redistributing tensor elements among computing units are described. In one aspect, a method includes distributing tensor elements of an N-dimensional tensor among multiple computing units of a computation system. Each computing unit redistributes the subset of tensor elements previously distributed to the computing unit to computing units. Each computing unit accesses redistribution partitioning data that specifies, for each computing unit, the tensor elements that are to be stored by the computing unit after redistributing the tensor elements. For each tensor element previously distributed to the particular computing unit, the computing unit determines a global linearized index value for the tensor element based on a multi-dimensional index for the tensor element.

Abstract: Methods, systems, and apparatus, including an apparatus for determining pixel coordinates for image transformation and memory addresses for storing the transformed image data. In some implementations, a system includes a processing unit configured to perform machine learning computations for images using a machine learning model and pixel values for the images, a storage medium configured to store the pixel values for the images, and a memory address computation unit that includes one or more hardware processors. The processor(s) are configured to receive image data for an image and determine that the dimensions of the image do not match the dimensions of the machine learning model. In response, the processor(s) determine pixel coordinates for a transformed version of the input image and, for each of the pixel coordinates, memory address(es), in the storage medium, for storing pixel value(s) that will be used to generate an input to the machine learning model.

Abstract: Methods, systems, and apparatus, including an apparatus for determining pixel coordinates for image transformation and memory addresses for storing the transformed image data. In some implementations, a system includes a processing unit configured to perform machine learning computations for images using a machine learning model and pixel values for the images, a storage medium configured to store the pixel values for the images, and a memory address computation unit that includes one or more hardware processors. The processor(s) are configured to receive image data for an image and determine that the dimensions of the image do not match the dimensions of the machine learning model. In response, the processor(s) determine pixel coordinates for a transformed version of the input image and, for each of the pixel coordinates, memory address(es), in the storage medium, for storing pixel value(s) that will be used to generate an input to the machine learning model.

Abstract: Methods, systems, and apparatus, including an apparatus for determining pixel coordinates for image transformation and memory addresses for storing the transformed image data. In some implementations, a system includes a processing unit configured to perform machine learning computations for images using a machine learning model and pixel values for the images, a storage medium configured to store the pixel values for the images, and a memory address computation unit that includes one or more hardware processors. The processor(s) are configured to receive image data for an image and determine that the dimensions of the image do not match the dimensions of the machine learning model. In response, the processor(s) determine pixel coordinates for a transformed version of the input image and, for each of the pixel coordinates, memory address(es), in the storage medium, for storing pixel value(s) that will be used to generate an input to the machine learning model.

Abstract: Methods, systems, and apparatus, including an apparatus for determining pixel coordinates for image transformation and memory addresses for storing the transformed image data. In some implementations, a system includes a processing unit configured to perform machine learning computations for images using a machine learning model and pixel values for the images, a storage medium configured to store the pixel values for the images, and a memory address computation unit that includes one or more hardware processors. The processor(s) are configured to receive image data for an image and determine that the dimensions of the image do not match the dimensions of the machine learning model. In response, the processor(s) determine pixel coordinates for a transformed version of the input image and, for each of the pixel coordinates, memory address(es), in the storage medium, for storing pixel value(s) that will be used to generate an input to the machine learning model.

Abstract: Embodiments of the video data capture and stream method comprise intercepting a flip function call comprising a call by the video application to flip frames between a display and a buffer, grabbing a copy of the current frame that would normally be processed by a central processing unit (CPU), placing the copy in a queue for processing by a graphics processing unit (GPU), wherein processing by the GPU is significantly faster than processing by the CPU.

Abstract: A connector assembly connects a plurality of battery cells in a serial/parallel arrangement. Each battery cell includes a cover and a canister having a side and a bottom. Each battery cell is constructed such that a segment of the side of the canister forms a top crimped portion that retains the cover and is electrically isolated from the cover. The connector assembly includes a conductive weld cup. The conductive weld cup includes a bordered portion and recessed portion. The bordered portion includes a first side wall and a ledge that is substantially planar. The recessed portion is recessed within the ledge. The recessed portion includes a recessed portion and a floor that is substantially planar. The first side wall includes an integrated tab projecting from it. An inner surface of the bordered portion engages an outer surface of the side and the bottom of the canister of an upper adjacent battery cell. An outer surface of the floor engages a cover of a lower adjacent battery cell.