Patents by Inventor Daniel Kinzer

Daniel Kinzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10868113
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 15, 2020
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Joseph A. Yedinak, Ashok Challa, Dean E. Probst, Daniel Kinzer
  • Publication number: 20180012958
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Application
    Filed: August 28, 2017
    Publication date: January 11, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Joseph A. YEDINAK, Ashok CHALLA, Dean E. PROBST, Daniel KINZER
  • Patent number: 9478519
    Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 25, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ahmad R. Ashrafzadeh, Vijay G. Ullal, Justin Chiang, Daniel Kinzer, Michael M. Dube, Oseob Jeon, Chung-Lin Wu, Maria Cristina Estacio
  • Publication number: 20160126219
    Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 5, 2016
    Inventors: Ahmad R. ASHRAFZADEH, Vijay G. ULLAL, Justin CHIANG, Daniel KINZER, Michael M. DUBE, Oseob JEON, Chung-Lin WU, Maria Cristina ESTACIO
  • Patent number: 9177925
    Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: November 3, 2015
    Assignee: Fairfchild Semiconductor Corporation
    Inventors: Ahmad R. Ashrafzadeh, Vijay G. Ullal, Justin Chiang, Daniel Kinzer, Michael M. Dube, Oseob Jeon, Chung-Lin Wu, Maria Cristina Estacio
  • Publication number: 20140312458
    Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.
    Type: Application
    Filed: November 27, 2013
    Publication date: October 23, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Ahmad ASHRAFZADEH, Vijay ULLAL, Justin CHIANG, Daniel KINZER, Michael M. DUBE, Oseob JEON, Chung-Lin WU, Maria Cristina ESTACIO
  • Patent number: 7557395
    Abstract: A trench power semiconductor device including a recessed termination structure.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: July 7, 2009
    Assignee: International Rectifier Corporation
    Inventors: Ling Ma, Adam Amali, Siddharth Kiyawat, Ashita Mirchandani, Donald He, Naresh Thapar, Ritu Sodhi, Kyle Spring, Daniel Kinzer
  • Publication number: 20070210333
    Abstract: A hybrid device including a silicon based MOSFET operatively connected with a GaN based device.
    Type: Application
    Filed: March 10, 2006
    Publication date: September 13, 2007
    Inventors: Alexander Lidow, Daniel Kinzer, Srikant Sridevan
  • Publication number: 20070194342
    Abstract: A substrate for a GaN based semiconductor device is formed by a poly SiC substrate having a thin sapphire layer on the top surface thereof Sapphire layer may be 0.1 to 1.0 microns thick. GaN type layers are then grown atop the sapphire layer with a transition layer between them if desired.
    Type: Application
    Filed: January 11, 2007
    Publication date: August 23, 2007
    Inventor: Daniel Kinzer
  • Publication number: 20070187750
    Abstract: A superjunction power semiconductor device which includes spaced drift regions each extending from the bottom of a respective gate trench to the substrate of the device.
    Type: Application
    Filed: January 24, 2007
    Publication date: August 16, 2007
    Inventor: Daniel Kinzer
  • Publication number: 20070085111
    Abstract: A power semiconductor device having a termination structure that includes a polysilicon field plate, a metallic field plate, and a polysilicon equipotential ring.
    Type: Application
    Filed: September 14, 2006
    Publication date: April 19, 2007
    Inventors: Jianjun Cao, Nazanin Amani, Daniel Kinzer
  • Publication number: 20070082480
    Abstract: Processes are described for forming very thin semiconductor die (1 to 10 microns thick) in which a thin layer of the upper surface of the wafer is processed with junction patterns and contacts while the wafer bulk is intact. The top surface is then contacted by a rigid wafer carrier and the bulk wafer is then ground/etched to an etch stop layer at the bottom of the thin wafer. A thick bottom contact is then applied to the bottom surface and the top wafer carrier is removed. All three contacts of a MOSFET may be formed on the top surface in one embodiment or defined by the patterning of the bottom metal contact.
    Type: Application
    Filed: September 8, 2006
    Publication date: April 12, 2007
    Inventors: Daniel Kinzer, Michael Briere, Alexander Lidow
  • Publication number: 20060237793
    Abstract: A cellular MOSgated device of planar or trench topology has base injection regions formed between pairs of cells to inject minority carriers to modulate the resistivity of the drift region.
    Type: Application
    Filed: April 20, 2006
    Publication date: October 26, 2006
    Inventors: Bruno Nadd, Daniel Kinzer
  • Publication number: 20060181332
    Abstract: A voltage supply circuit for providing an output DC voltage from an input DC voltage bus that includes a III-nitride based power semiconductor device series connected between the input DC voltage bus and an output capacitor, which is switchable from an on state to an off state in order to charge up the output capacitor.
    Type: Application
    Filed: February 2, 2006
    Publication date: August 17, 2006
    Inventor: Daniel Kinzer
  • Publication number: 20060175633
    Abstract: A III-nitride power device that includes a Schottky electrode integrated with a power switch. The combination is used in power supply circuits such as a boost converter circuit.
    Type: Application
    Filed: February 2, 2006
    Publication date: August 10, 2006
    Inventor: Daniel Kinzer
  • Publication number: 20060081985
    Abstract: A III-nitride power semiconductor device that includes a current sense electrode.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 20, 2006
    Inventors: Robert Beach, Paul Bridger, Daniel Kinzer
  • Publication number: 20060043474
    Abstract: A trench type top drain MOSgated device has a drain electrode on the die top and a source electrode on the die bottom surface. The device is turned on by a control voltage connected between a drain and a gate region. The device cell has a body short trench and a gate trench. Gate poly is disposed in the bottom of the gate trench and is disposed adjacent a thin gate oxide lining a channel region with minimum overlap of the drain drift region. The bottom of the body short trench contains a contact which shorts the body region to the channel region. The body short, top drain region and gate polysilicon are simultaneously silicided. The gate trench is widened at its top to improve Qgd characteristics. Both the body short trench and gate trench are simultaneously filled with gap fill material.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 2, 2006
    Inventors: Daniel Kinzer, David Jones, Kyle Spring
  • Publication number: 20050230777
    Abstract: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.
    Type: Application
    Filed: March 4, 2005
    Publication date: October 20, 2005
    Inventors: Davide Chiola, He Zhi, Kohji Andoh, Daniel Kinzer
  • Publication number: 20050224870
    Abstract: A trench type power semiconductor device includes a channel region atop an epitaxially silicon layer and a plurality of shallow gate electrode trenches within the channel region such that the bottom of each trench extends to a distance above the junction defined by the channel region and epitaxially silicon layer. Formed at the bottom of each trench within the channel region are trench tip implants of the same conductivity as the epitaxial silicon layer. The trench tip implants extend through the channel region and into the epitaxially silicon layer. The tips effectively pull up the drift region of the device in a localized fashion. In addition, an insulation layer lines the sidewalls and bottom of each trench such that the insulation layer is thicker along the trench bottoms than along the trench sidewalls. Among other benefits, the shallow trenches, trench tips, and variable trench insulation layer allow for reduced on-state resistance and reduced gate-to-drain charge.
    Type: Application
    Filed: February 28, 2005
    Publication date: October 13, 2005
    Inventor: Daniel Kinzer
  • Patent number: RE41719
    Abstract: A driver stage consisting of an N channel FET and a P channel FET are mounted in the same package as the main power FET. The power FET is mounted on a lead frame and the driver FETs are mounted variously on a separate pad of the lead frame or on the main FET or on the lead frame terminals. All electrodes are interconnected within the package by mounting on common conductive surfaces or by wire bonding. The drivers are connected to define either an inverting or non-inverting drive.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: September 21, 2010
    Assignee: International Rectifier Corporation
    Inventors: Daniel Kinzer, Tim Sammon, Mark Pavier, Adam Amali